The document describes a 128-bit low power and area efficient carry select adder design. It proposes using a binary to excess-1 converter instead of a ripple carry adder for the carry select adder, which can reduce area and power consumption. Simulation results show the modified 128-bit carry select adder design achieves a 15.48% reduction in area and 7.41% reduction in power compared to a regular carry select adder design.