implementation and comparision of effective area efficient architecture for CSLA
1. Implementation and
Comparison of Effective Area
Efficient Architectures for
CSLA
Presented by:
N Venkatesh(13Q91A04A6)
Sunketa Ravi(13Q91A0490)
S Sandeep (13Q91A0491)
Under the Esteemed Guidance Of:
Sri K.RAJESHWAR
2. CONTENTS
ABSTRACT
INTRODUCTION
EXISTING SYSTEM
PROPOSED SYSTEM
COMPARISION
RTL SCHEMATIC
SIMULATION RESULT
ADVANTAGES
TOOL USED
CONCLUSION
3. ABSTRACT
Carry Select Adder (CSLA) is one of the fastest adders used in
many data-processing processors to perform fast arithmetic
functions.
By gate level modification of CSLA architecture we can reduce area
and power.
Based on this modification 16-bit square-root CSLA (SQRT CSLA)
architecture have been developed.
The proposed design has reduced area and power as compared with
the regular SQRT CSLA .
4. INTRODUCTION
In electronics, an adder or summer is a digital circuit that performs
addition of numbers.
Adders can be constructed for many numerical representations, such
as BCD or Excess-3, the most common adders operate on binary
numbers.
Adders plays Major role in Multiplications and other advanced
processers designs
5. EXISTING SYSTEM
The carry-select adder generally consists of two Ripple Carry adders
(RCA) and a Multiplexer .
Adding two n-bit numbers with a carry-select adder is done with two
adders (therefore two RCA).
In order to perform the calculation twice, one time with the
assumption of the carry being zero and the other assuming one.
7. AREA EVALUATION METHODOLOGY OF REGULAR 16-b
SQRT CSLA
Gate count=
57(HA+FA+MUX)
FA=39(3*13)
HA=6(1*6)
MUX=12(3*4)
8. PROBLEMS IN EXISTING SYSTEM
The problem in CSLA design is the number of full adders are increased then
the circuit complexity also increases.
The number of full adder cells are more thereby power consumption of the
design also increases
Number of full adder cells doubles the area of the design also increased.
9. SOLUTION OF THE PROBLEM
The parallel RCA with Cin=1 is replaced with Binary-Excess 1
converter( BEC).
fig: four-bit BEC
10. PROPOSED SYSTEM(16-bit CLSA)
In this system we use the BEC to reduce the RCA circuits
Here based on the carry input the MUX will be select corresponding
input
In this design we give the MUX inputs are RCA output and BEC
output
Compare to regular design the area of the design is less
19. ADVANTAGES
Low power consumption
Less area (less complexity)
More speed compare regular CSLA
20. CONCLUSION
A simple approach is proposed in this paper to reduce the area and power
of SQRT CSLA architecture. The reduced number of gates of this work
offers the great advantage in the reduction of area and also the power. The
modified CSLA architecture is therefore, low area, low power, simple and
efficient for VLSI hardware implementation.