1. CSIR-NAL
MTechProjectReview
1
CSIR-NAL
By
SG Ramanathan
MTech Thesis Project
Final Submission
External Review

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MTechProjectReview
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Title of Project Thesis
Design and Development of
Graphics Processing Unit (GPU) Framework
on FPGA
Target FPGA - Spartan-6
XC6SLX45T-3FGG484
Internal Guide
Mr. JAYAKUMAR EP
Asst. Professor
Department of ECE
NIT, Calicut
External Guide
Dr. ANANDA CM
Sr. Principal Scientist
Head, Aerospace Electronics
Systems Division
CSIR-NAL, Bangalore

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MTechProjectReview
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Agenda
Scope & Objective of the Project
System Overview
Triple Video Buffers
DDR3 Memory Controller Integration
Host Application Development
Results & Conclusion
Summary
Rendering Algorithm
Video Demonstration
Design Blocks Interface

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Scope & Objective Of Project
Develop GPU Frame Work Functionalities
FPGA – VHDL
Triple Video Buffer Mechanism
Display Graphics Controller Design
Develop Rendering Algorithm
Host Application – ‘C’ Program
Command Generation
LCD Display
Design Output
Socket Programming UDP Packet Decoder

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UDP Decoder
Pixel
Color/Command
Handler
DDR3
Memory
Triple Buffer
Handler
Display
Controller
Typical GPU
Interfaces
Top-Level FPGA Blocks
Host
Machine
Display
System
Frame Rendering:
Converting Numeric
Coordinates into bitmaps
Graphics Controller:
Converting Bitmaps into
signals for screen with
control signals based on
the chosen resolution
Buffer Management: Frame
Buffering using Triple
Display Buffers

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System Overview
TEMAC
Core
FIFO
[FWFT]
UDP
Decoder
ARP Packet Transmitter
Colour
Data/
Command
Handler
[MIG
Wrapper]
MIG
Core
Flush
Buffer
Logic
FIFO
[FWFT]
Display
Buffer
Logic
FIFO
[STD]
XGA
Display
Controller
DDR3
Memory
Rasterization
Programming
in Host
Machine
TEMAC
Interface
Command
Memory
Interface
MIG Interface &
Triple Buffer
Implementation
Display
Controller
Review#1Review#2Review#3
Xilinx’s TEMAC - Tri-Mode Ethernet Media Access Controller

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Display Controller Design
& its Simulation Results

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XGA_
Generator
Clk_65 RGB
HSync
VSync
DDR3
Memory
 RGB with control signals
generated for fixed pattern/color
 Display pixels has been feed from
DDR3 memory
Graphics Controller: Converting Bitmaps
into signals for screen with control
signals for chosen resolution
Pixel Mapping: Each Pixel of the screen
mapped to a DDR3 memory location
Active Data

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Simulation Result#1: Display Controller Design
RGB Data in
Active Region

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DDR3 Memory Controller Integration
& its Simulation Results

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DDR3 Memory Read & Write Blocks
Input
Wrapper
Output
Wrapper
Spartan6 FPGA
MIG Wrapper
Memory
Controller
CORECmd_
FIFO
DATA
FIFO
DDR3
Memory
Memory Interface is a free software tool used to
generate memory controllers and interfaces
for Xilinx FPGAs
Top Design
Read & Write
Logics
Xilinx’s Memory Interface Controller Physical Component
in Board
 Command FIFO holds
Starting Address & Length
of Data
 Data FIFO holds Pixel color
(RGB)

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FSM for DDR3 Memory Access
START
Initialize all
Counters/
Register
Memory
Calibration
Status
Send Command to
Controller for Writing to
DDR3
Controller’s
Data FIFO
Empty
Write into Data FIFO
Increment Address to Next
Location
Write Finish
Status
STOP
Completed
Not
Completed
Empty
Not
Empty
Finished
Not
Finished
START
Initialize all
Counters/
Register
Memory
Calibration
Status
Send Command to
Controller for Reading
DDR3
Controller’s
Data FIFO
Full
Read Data FIFO Content
Increment Address to Next
Location
Read Finish
Status
STOP
Completed
Not
Completed
FULL
Not
FULL
Finished
Not
Finished
WRITE READ

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Simulation Result#2: DDR3 Memory Write Sequence
64 colors
Command
64 colors
Command
64 colors
Command

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Simulation Result#3: DDR3 Memory Read Sequence
Command
64 colors
Command
64 colors

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Triple Video Display Frame Buffer
Design

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DDR3 Memory
GPU Engine
What is Triple Display Frame Buffer?
Frame Buffer Display
 Operational Buffer: Dedicated Buffer for drawing the
frame content
 Display Buffers: Buffer the frame for display

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Triple Display Buffer Design – How It Works?
Operational Buffer
Memory Region
Display Buffer1
Display Buffer2
Display Buffer3
Port 2
Colour Data/
Command Handler
Port 5
Tri-Buffer
Display
Wrapper
Port 3
Port 4
Flush Logic
Wrapper
On
Vsync_Trigger
On Flush
Trigger
XGA Video
Generator
 Operational Buffer: Dedicated Buffer for drawing
the frame content
 Display Buffers: Buffer the frame for display

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Top
Design
PORT_2
PORT_3
PORT_4
PORT_5
RGB
Input
Wrapper
Tri_Buffer_
Display
Output
FIFO
Flush
Logic
Clock
Infrastructure
Spartan 6FPGA
Wrapper
Memory
Controller
CORE
Cmd_
FIFO
DATA
FIFO
Clk_200
All Clock Signals
for Memory
Controller Design
Clock Gen IP
Clk_125
Clk_65
Clk_333.33
DDR3
Memory
Clk_333.33
XGA_
Generator
FLUSH
Latest
Buffer’sBase
Address
Vsync_Pulse
Integrated Design with Triple Buffer - FPGA

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Host Machine Interface & Application
Development

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Host Software Application Design Functions
User Inputs/Commands
Rendering Algorithm
Slice Packets
Chop-Off
Socket Program
Coordinates, Colour
Dot, Line, Arc Primitives
64 Word Count
Ignore Over shoot pixels
Ethernet Protocol
UDP Decoder
Pixel
Color/Command
Handler
DDR3
Memory

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Host – FPGA Ethernet Interface
Host
Machine
UDP Packet
ARP Packet
FPGA Host Machine & FPGA are bonded with IP & MAC ID’s
Ethernet Data
Payload Structure

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Drawing Pixel Dots
𝐷𝐷𝑅3 𝑀𝑒𝑚𝑜𝑟𝑦𝐿𝑜𝑐𝑎𝑡𝑖𝑜𝑛 = 1024 ∗ 𝑦 𝑜𝑓𝑓𝑠𝑒𝑡 + 𝑥 𝑜𝑓𝑓𝑠𝑒𝑡
 Memory Address for given 𝑥 𝑐𝑜𝑜𝑟𝑑𝑖𝑛𝑎𝑡𝑒&𝑦 𝑐𝑜𝑜𝑟𝑑𝑖𝑛𝑎𝑡𝑒
On Screen

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Line is a Stair-Case

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Bresenham’s Line Algorithm
2 3 4 5
2
4
3
5
(xk, yk)
(xk+1, yk)
(xk+1, yk+1)
y
yk
yk+1
xk+1
dlower
dupper
 Algorithm finds pixel closer to original line
 0<=Slope<=1 is standard Bresenham’s Algorithm
 Slope > 1 & Slope < 0 are derived from Bresenham’s Algorithm

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Line Slopes
0<Slope<=1Slope>1

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Slope=0Slope<0
Line Slopes

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Chop-Off Overshoot Pixels
Commanded Without Chop-Off With Chop-Off
Chop-Off - R
Chop-Off - L
OnScreen
 Shift the starting point to left edge of the screen
 Chop-Off the overshoot pixels
Algorithms Built to:

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Final Integrated
Design with Clock
Sources
Command Decoder
(Ethernet Packet)
Triple Buffer Memory
Management
Display Controller Design

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Evaluation Platform
SP605 Board –
Spartan 6 FPGA
Host Machine
LCD Display
Dials&Pointer
Symbology

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Results on Target FPGA
 Basic Primitives like dots, blocks and lines with different slopes
on final integrated display

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Results on Target FPGA
 Lines with different slopes to form circle like structure
 Proves the capabilities of Bresenham’s Line Algorithm

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Results on Target FPGA
 Aircraft Display Parameters (Torque, ITT) are represented
using Dials & Pointers symbology
 Derived from Bresenham’s Line Algorithm

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Video Demonstration
Triple Buffer Operation
Primitives & Dials on Display

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Summary
 GPU frame work on FPGA
has been realized
successfully for Avionics
Applications.
IEEE Conference Paper
Acceptance Notification Received
 Recent Trends in Electronics,
Information & Communication
Technology (RTEICT 2016)

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 To Fulfill Real World GPU Demands more functionalities like:
 Derived objects relevant for avionics field.
 Anti-Aliasing (adjusting pixel intensities along the line path to smooth raster
lines)
 Blending
 Overlay Additional Information on top current frame
 Multi-Layer Implementation with addition of memory buffers
 Pipelining (Process multiple commands instead of single at a time)
 Migrate Rasterization functionalities also in FPGA (HDL) program
Future Work - Extended

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[1] Rapid Prototyping of Digital Systems, SOPC Edition, James O. Hamblen, Tyson S. Hall,
Michael D. Furman, Springer – 2008 Edition.
[2] www.ijettjournal.org/volume-14/number-6/IJETT-V14P251.pdf
[3] http://blog.digitalelectronics.co.in/2008/09/simple-xvga-1024x768-controller-in.html
[4] is.muni.cz/th/150871/fi_m/Masters_Thesis.pdf
[5] http://www.edn.com/electronics-blogs/dev-monkey-blog/4408548/Minimizing-Video-
Processing-Design-Time-with-FPGA-Development-Kits-and-Reference-Designs-4408548
[6] www.xilinx.com/support/documentation/user_guides/ug388.pdf
[7] https://docs.oracle.com/javase/tutorial/extra/fullscreen/doublebuf.html
References

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Discussion

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Back-Up Slides

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MTechProjectReview
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Operational Buffer Triple Buffers
Draw Frame
Flush
Clear
Operational Buffer Triple Buffers
Draw Frame
Flush
Clear
Asynchronous Buffer Operations - Animation
Host Machine FPGA Display System

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Display
Controller
Board
* For LVDS Signal
Generation in
Display Resolution
Format
* Resolution based
UP or DOWN
scaling
Video
Design
Controller
DVI Chip on
FPGA
Board
HDMI VGA
LVDS
Signal is
Serial
Data of
6 lines
CLK
Parallel Data gets converted into
Serial Data by using LVDS Format to
avoid delay
VSync
HSync
Parallel
Data LCD Panel
Controller
(It has V_count &
H_count resets
based on Vsync &
Hsync signals)
CLK
DISPLAY PANELFPGA Board
RGB
VSync
Rest of
Designs
Interfaces: Display Controller Design and Display Panel Controllers

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architecture Behavioral of VSync_Postive_Edge is
signal v_signal:std_logic:='0';
begin
p:process(clk,V_sync_in)
begin
if(clk = '1' and
clk'event ) then
v_signal <= V_sync_in;
end if;
end process p;
V_sync_pos_out <= not(v_signal) and V_sync_in;
Flip
Flop
architecture Behavioral of VSync_Postive_Edge is
signal v_signal:std_logic:='0';
begin
p:process(clk,V_sync_in)
begin
if(clk = '1' and
clk'event ) then
v_signal <= V_sync_in;
end if;
end process p;
V_sync_pos_out <= v_signal and not (V_sync_in);
Flip
Flop
Edge (Positive & Negative) Detect Process

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Difference: Writing FIFO & DDR3 Memory

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ICON Core & Chip Scope Pro Analyzer Interfaces
Chip Scope
ICON
Integrated Logic
Analyzer (ILA)
Virtual IO (VIO)
AXI Monitor
Agilent Trace
Core2 (ATC2)
JTAG
Boundary
Scan
(BSCAN)
FPGA User
Design Circuitry
Chip Scope
Pro Analyzer
in Host
Computer
Debug
.cdc
File
VIO.xco &
ICON.xco
File
ChipScopeProCores

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ILA Core and Analyzer Interface
Chip
Scope
ICON
Integrated
Logic Analyzer
(ILA)JTAG
Boundary
Scan
(BSCAN)
FPGA User
Design
Circuitry
Chip Scope Pro
Analyzer in
Host Computer
Debug
.cdc
File
Debug
.cdc
File
• Select ILA
• Select interested Signals to Monitor
• Make Connections (Signals & Clock)

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ILA Signal Triggers

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Triple Display Buffer Design – With Break Point
Operational Buffer
Memory Region
Display Buffer1
Display Buffer2
Display Buffer3
Port 2Input Wrapper
Port 5
Tri-Buffer
Display
Wrapper
Port 3
Port 4
Flush Logic
Wrapper
On
Vsync_Trigger
XGA Video
Generator
Set pattern -1
Pattern -1

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CSIR-NAL
Operational Buffer
Memory Region
Display Buffer1
Display Buffer2
Display Buffer3
Port 2Input Wrapper
Port 5
Tri-Buffer
Display
Wrapper
Port 3
Port 4
Flush Logic
Wrapper
On
Vsync_Trigger
On Flush
Trigger
Flush pattern -1
XGA Video
Generator
Pattern -1
Pattern -1
Pattern -1
Pattern -1
Triple Display Buffer Design – With Break Point

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CSIR-NAL
Operational Buffer
Memory Region
Display Buffer1
Display Buffer2
Display Buffer3
Port 2Input Wrapper
Port 5
Tri-Buffer
Display
Wrapper
Port 3
Port 4
Flush Logic
Wrapper
On
Vsync_Trigger
XGA Video
Generator
Set pattern -2
Pattern -2
Pattern -1
Triple Display Buffer Design – With Break Point

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CSIR-NAL
Operational Buffer
Memory Region
Display Buffer1
Display Buffer2
Display Buffer3
Port 2Input Wrapper
Port 5
Tri-Buffer
Display
Wrapper
Port 3
Port 4
Flush Logic
Wrapper
On
Vsync_Trigger
On Flush
Trigger
Flush pattern -2
XGA Video
Generator
Pattern -2
Pattern -2
Pattern -2
Pattern -2
Triple Display Buffer Design – With Break Point

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CSIR-NAL
Operational Buffer
Memory Region
Display Buffer1
Display Buffer2
Display Buffer3
Port 2Input Wrapper
Port 5
Tri-Buffer
Display
Wrapper
Port 3
Port 4
Flush Logic
Wrapper
On
Vsync_Trigger
XGA Video
Generator
Set pattern -3
Pattern -3
Pattern -2
Triple Display Buffer Design – With Break Point

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CSIR-NAL
Operational Buffer
Memory Region
Display Buffer1
Display Buffer2
Display Buffer3
Port 2Input Wrapper
Port 5
Tri-Buffer
Display
Wrapper
Port 3
Port 4
Flush Logic
Wrapper
On
Vsync_Trigger
On Flush
Trigger
Flush pattern -3
XGA Video
Generator
Pattern -3
Pattern -3
Pattern -3
Pattern -3
Triple Display Buffer Design – With Break Point

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CSIR-NAL
Operational Buffer
Memory Region
Display Buffer1
Display Buffer2
Display Buffer3
Port 2Input Wrapper
Port 5
Tri-Buffer
Display
Wrapper
Port 3
Port 4
Flush Logic
Wrapper
On
Vsync_Trigger
XGA Video
Generator
Set pattern -4
Pattern -4
Pattern -3
Triple Display Buffer Design – With Break Point

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CSIR-NAL
Operational Buffer
Memory Region
Display Buffer1
Display Buffer2
Display Buffer3
Port 2Input Wrapper
Port 5
Tri-Buffer
Display
Wrapper
Port 3
Port 4
Flush Logic
Wrapper
On
Vsync_Trigger
On Flush
Trigger
Flush pattern -4
XGA Video
Generator
Pattern -4
Pattern -4
Pattern -4
Pattern -4
Triple Display Buffer Design – With Break Point

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Top Design
Output
FIFO
Spartan 6FPGA
Wrapper
Memory
Controller
CORE
Cmd_
FIFO
DATA
FIFO
PORT_3
PORT_2
DDR3
Memory
MIG Clock
Generation
Clk_200
All Clock Signals
for Memory
Controller Design
Clock Gen IP
Clk_125
Clk_65
Clk_333.33
Clk_333.33
XGA_
Generator
RGB
HSync
VSync
Input
Wrapper
Output
Wrapper
Integrating
DDR3 with
Video Generator

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Proposed Thesis Schedule

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XGA Resolution 1024 x 768: Control Signals
 Populate Color Pixel Data in ACTIVE AREA to Make them Visible in a Frame
H_Count
V_Count
 V_Sync is indication of START of FRAME

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On Target: Display Controller Design
Static Color Generation using Display
Controller Design

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64 Data
64 Data
64 Data
64 Data
64 Data
One Shot Write
of 64 Data
St_addr. To write
Keep
incrementing 64
every time up to
limit of total Pixel
value
Memory
Controller
DATA FIFO
(64 Depth)
CMD
FIFO
Port 2
Memory
Controller
DATA FIFO
(64 Depth)
CMD
FIFO
Port 3
St_addr. To Read
Keep
incrementing 64
every time up to
limit of total Pixel
value
One Shot Read
of 64 Data
One Shot Write
of 64 Data
St_addr. To write
Keep
incrementing 64
every time up to
limit of total Pixel
value
St_addr. To Read
Keep
incrementing 64
every time up to
limit of total Pixel
value
One Shot Read
of 64 Data
DDR3 Memory Read & Write Sequence
Input
Wrapper
Output
Wrapper
WRITE READ

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DDR3 Memory
GPU Engine
What is Triple Display Frame Buffer?
Frame Buffer Display
 Operational Buffer: Dedicated Buffer for drawing the
frame content
 Display Buffers: Buffer the frame for display
We can’t clear the display between each frame of data written into display; So last frame of information
gets retained along with current frame of information, may lead to flicker
Chances of have Half-screen with old data and remaining with new data; sometimes we may miss
some frames in between in case of FPS is higher
Layering implementation is impossible with this single operational buffer, which is mandate for
aerospace display application development
If 1 Buffer
If 2 Buffers
If 3 Buffers

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Chop-Off Overshoot Pixels