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INDIAN KARTING RACE
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Imperial Society
of Innovative
Engineers
Presents
INDIAN KARTING RACE (IKR 2018)
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INDEX
Topic Page Number
Part I – ADMINISTRATIVE RULES
1. Introduction 4-6
2. Registration Requirement 7-9
3. Driver’s Requirement 8
4. Kart Eligibility 9
5. Registration Process and Deadlines 10-12
Part II – JUDGING CRITERIA
1. Pre Virtual Round 13
2. Virtual Round 13-16
3. College level Technical Inspection 16
4. Deadline and Penalties 16
5. Web based Submission 16
6. Event Points 17
7. Award List 18
PART III – TECHNICAL RULES
Vehicle Categories 20
1. Chassis Design Restriction 21-25
2. Wheels and Tyres 25-26
3. Driver’s Compartment 26
4. Steering 28
5. Braking 28-30
6. Power Unit and Transmission 30-32
7. Safety Measurements 33-36
8. Bodyworks 36-37
9. Compulsory Advertisement 37
PART IV – DYNAMIC ROUND
1. Dynamic Round Registration 38
2. Briefings 38
3. Photo Session/ Media 38-39
4. Static Event 39-40
5. Dynamic Event 41-43
6. Flags 43-44
PART V – DRIVER’S HANDBOOKS
1. Driver’s Requirement 45
2. Driver’s Equipment 45-46
3. Code of Conduct during event 46-47
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ADMINISTRATIVE RULEBOOK
1. Introduction:
1.1. About ISIE:
Imperial Society of Innovative Engineers are well known Society of India for organizing
Motorsports events, live projects based Industrial Training and Research and publication.
ISIE – India provides a platform to the students and professionals for development and
enhancement of their technical as well as managerial skills. We are developing platform
especially for engineering students where they can easily face real-time engineering
problems and find the best solution, especially in the sector of Electric and Hybrid Vehicles.
ISIE - India is the India’s best platform for the engineering students to develop practical
skills. We believe in “Learning, Implementation, and Sharing”. The Society has a very strong
placement and consultancy wing that has an excellent network of the top companies.
Our core competencies include effective personalized industry based training and excellent
placements. ISIE is committed to the development in the field of renewable source of
energy; these are the best solution to save our environment and development of our
country. We are organizing Hybrid and Go Kart National and International event.
Our Accreditations:
Federation of Motor Sports Club of India (FMSCI) –
The FMSCI is recognized by the Government of India, Ministry of Youth Affairs and Sports as
the only National Sports Federation (NSF) for the promotion and governance of motorsports
in India. The FMSCI is also a long-standing member of the International Federations for
motorsports viz. Federation International de l' Automobile (FIA), Paris (four wheelers and
above) and Federation International de Motocyclisme (FIM), Geneva (2 and 3 wheeler
motorsports).
The FMSCI is also a member of the Indian Olympic Association. The FMSCI has a wide base
of affiliated member clubs spread across India.
ISO 9001:2008:
ISIE Awarded ISO 9001:2008 certifica
2. Course Outcome
After the completion of course student will be able to
CO1 Understand the requirements of VHDL design flow
CO2 Interpret the Verilog language elements and its relevance to
digital design
CO3 Apply the Modelling Styles for Simulation, Synthesis and
Test Bench Creation.
CO4 Analyse the Performance Study of Combinational and
Sequential logic design using Verilog
CO5 Evaluate State Machine and Memory designs by Verilog
CO6 Create and realize the system in FPGA using Verilog
3. UNIT 5
REALIZING APPLICATIONS IN FPGA
FPGA Design Flow - Architecture of Xilinx Artix7 FPGA - Configurable Logic Blocks
(CLB)- Slice Description- LUT - Storage element - Programmable Interconnect -
Internal Hard macros - Realizing applications in FPGA - combinational functions -
N-bit functions, Encoder, Decoders - Sequential functions - N-bit register, shift
registers, up/down counters- N-bit processor. Case Study: study of protocols I2C,
SPI and UART.
7. FPGA Design Translation
• CAD to translate circuit from text description to physi
cal implementation
• Most current FPGA designers use register-transfer l
evel specification
RTL
.
.
C = A+B
.
Circuit
A
B
+ C
Array
8. Register Transfer-Level Design
• A register-transfer machine has combinational logic connecting
registers:
D
Q Combinational
Logic
D Q
D Q Combinational
Logic
Combinational
Logic
9. Lect-14.9
FPGA Circuit Compilation
• Technology Mapping
• Placement
• Routing
LUT
LUT
Assign a logical LUT to a physical location
Select wire segments and switches for
interconnection
11. Lect-14.11
Design Flow with Test
Design and implement a simple unit permitting to speed
up encryption with RC5-similar cipher with fixed key set
on 8031 microcontroller. Unlike in the experiment 5, this
time your unit has to be able to perform an encryption
algorithm by itself, executing 32 rounds…..
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RC5_core is
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31 downto 0);
data_output: out std_logic_vector(31 downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31 downto 0);
key_read: out std_logic;
);
end RC5_core;
Specification
VHDL
description
Functional simulation
Post-synthesis simulation
Synthesized
Circuit
12. Lect-14.12
Design Flow with Test (cont.)
Implementation
Configuration
Timing simulation
On chip testing
Post-synthesis simulation
Synthesized
Circuit
16. Lect-14.16
Configuration
• Once a design is implemented, you must create a file that the
FPGA can understand
• This file is called a bit stream: a BIT file (.bit extension)
• The BIT file can be downloaded directly to the FPGA, or can be
converted into a PROM file which stores the programming
information
17. Consists of…
• Real 6-input look-up table (LUT) technology
• Dual LUT5 (5-input LUT) option
• Distributed Memory and Shift Register Logic capability
• Dedicated high-speed carry logic for arithmetic functions
• Wide multiplexers for efficient utilization
7 series configurable logic block (CLB)
➢ CLBs are the main logic resources for implementing sequential as well as
combinatorial circuits
➢ Each CLB element is connected to a switch matrix for access to the
general routing matrix
