Multiplexers and demultiplexers allow digital information from multiple sources to be routed through a single line. A multiplexer has multiple data inputs, select lines to choose an input, and a single output. A demultiplexer has a single input, select lines to choose an output, and multiple outputs. Bigger multiplexers and demultiplexers can be built by cascading smaller ones. Multiplexers can implement logic functions by using the select lines as variables and routing the input lines to the output.

1. Multiplexer (data Selectors)
• Definition : A multiplexers (MUX) is a device that allows digital
information from several sources to be routed onto a single
line for transmission over that line to a common destination.
• Several data input lines
• Some select line (less than the no. of input lines)
• Single output line
• If there are n data input lines and m select lines, then
2m
= n

2. Functional Diagram Of a Multiplexer

3. 2 : 1 Multiplexer
S Z
0 I0
1 I1

4. 4 : 1 Multiplexer
S0 S1 Z
0 0 I0
0 1 I1
1 0 I2
1 1 I3

5. 8 : 1 Multiplexer
S0 S1 S3 Z
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

6. Multiplexer Tree
• The Multiplexers with more number of inputs can be obtained by
cascading two or more multiplexers with less number of inputs.
• Below is a design of 16:1 MUX using 4 4:1 MUXs :-

7. Demultiplexer (Data Distributor)
• Definition : A DEMULTIPLEXER (DEMUX) basically reverses
the multiplexing function. It takes data from one line and
distributes them to a given number of output lines. For this
reason, the demultiplexers is also known as a data
distributor.
• Single data input lines
• Some select line (less than the no. of output lines)
• Several output line
• If there are n data output lines and m select lines, then
2m
= n

8. Functional Diagram Of a Demultiplexer

9. 1 : 2 Demultiplexer
S0 Y0 Y1
0 D 0
1 0 D

10. 1 : 4 Demultiplexer
S0 S1 D0 D1 D2 D3
0 0 D 0 0 0
0 1 0 D 0 0
1 0 0 0 D 0
1 1 0 0 0 D

11. 1 : 8 Demultiplexer

12. 1 : 8 Demultiplexer (Truth Table)
S0 S1 S3 D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 D 0 0 0 0 0 0 0
0 0 1 0 D 0 0 0 0 0 0
0 1 0 0 0 D 0 0 0 0 0
0 1 1 0 0 0 D 0 0 0 0
1 0 0 0 0 0 0 D 0 0 0
1 0 1 0 0 0 0 0 D 0 0
1 1 0 0 0 0 0 0 0 D 0
1 1 1 0 0 0 0 0 0 0 D

13. Demultiplexer Tree
F0 F1 F3F2 F4 F5 F6
F7
S0
S1
S2
1:2 Demux
1:2 Demux
1:2 Demux
1:2 Demux
1:2 Demux
1:2 Demux 1:2 Demux
INPUT
0 1
0
0
0
0
0
0
1
1
1
1
1 1
S
S
S
S
S
S
S
Below is a design of 1:8 MUX using 7 1: MUXs :-

14. Implementation Of Logic Functions
using Multiplexer
A B C F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
f(a, b, c) = a’b’c + ab
0
0
0
1
0
0
1
1
A B C
S2 S0S1
F
8:1 MUX
0
4
3
1
2
5
6
7

15. A B C O F
0 0 0 0
C
0 0 1 1
0 1 0 0
0
0 1 1 0
1 0 0 0
0
1 0 1 0
1 1 0 1
1
1 1 1 1
C
0
0
1
B C
S0S1
F
4:1 MUX
0
1
2
3
f(a, b, c) = a’b’c + ab

16. A B C D O F
0 0 0 0 0
D
0 0 0 1 1
0 0 1 0 0
D
0 0 1 1 1
0 1 0 0 1
D’
0 1 0 1 0
0 1 1 0 0
0
0 1 1 1 0
1 0 0 0 0
0
1 0 0 1 0
1 0 1 0 0
D’
1 0 1 1 1
1 1 0 0 1
1
1 1 0 1 1
1 1 1 0 1
1
1 1 1 1 1
f(a, b, c) = F=A’B’C’D + A’B’CD + A’BC’D’ + AB’CD +
ABC’D’ + ABC’D + ABCD’ +ABCD
D
0
1
A B C
S2 S0S1
F
8:1 MUX
0
4
3
1
2
5
6
7
D’

17. THANK YOU