VHDL can be used to describe electronic hardware at many different levels of abstraction

1. LEVEL OF ABSTRACTION
Prof. Sushil Ramchandra Sankpal
Sant Gajanan Maharaj College of Engineering
Mahagaon

2. DIAGRAM
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3. LEVELS OF ABSTRACTION FOR VHDL
 VHDL can be used to describe electronic hardware at
many different levels of abstraction
 VHDL has three levels of abstraction
1. Algorithm Level
2. Register Transfer Level (RTL)
3. Gate Level.
 Algorithms are unsynthesizable.
 RTL is the input to synthesis.
 Gate level is the output from synthesis.
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5. ALGORITHM LEVEL
 A pure algorithm consists of a set of
instructions that are executed in sequence to
perform some task, hence has neither
a clock nor detailed delays.
 The VHDL input may have to be constrained
in some artificial way for some synthesis tools,
perhaps through the presence of an ‘algorithm'
clock. So the operations in the VHDL code can
then be synchronized to this clock.
 Functions, Tasks are the main elements.
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6. REGISTER TRANSFER LEVEL (RTL)
 An RTL description has an explicit clock and
all operations are scheduled to occur in
specific clock cycles, but there are no detailed
delays below the cycle level.
 A single global clock may be preferred.
Retiming is a feature that allows operations to
be re-scheduled across clock cycles.
 RTL specifies the characteristics of a circuit by
operations and the transfer of data between
the registers.
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7. GATE LEVEL
 A gate level description consists of a network
of gates and registers instanced from a
technology library, which contains technology-
specific delay information for each gate.
 The characteristics of a system are described
by logical links and their timing properties.
Signals have discrete logic values like
(‘0’,’1’,’X’,’Z’). Gate level Primitives can be used
to model the design.
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8. Thank You..
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