1. Curriculum Vitae
Name: David Watling
Company: NVIDIA (Icera department)
Position: Test Development Engineer
Address: 'Clifton'
Bath Road
Devizes
Wiltshire
SN10 2AY
Telephone: Home - 01380 724726
Work –
Email: watlingnursoo@btinternet.com
Date of Birth: 12 August 1965
Education: September 1978 to July 1983 - Clifton College, Bristol.
October 1984 to July 1988 - Edinburgh University.
Qualifications: 'O' levels: 13
'A' levels: 4 - Physics (A)
Maths (B)
Chemistry (B)
Music (E)
Degree: Electronics & Electrical Engineering (BSc Hons).
Achievements: Cross - Country Champion (Clifton College).
Private Pilots Licence.
Hobbies: Electronics, DIY, plumbing, Motor Maintenance + Welding, Music (Guitar, Cello,
Horn, Drums), Computing.

2. Work Experience
Dates: May. 2005 - present.
Company: NVIDIA/Icera Semiconductor, Bristol.
Domain: 3G/4G Microprocessor and firmware solution – HS datacards.
Position: Test Development Engineer (permanent).
Details: I was originally hired as a Vee programmer with RF test experience. My first task
(6 months) was to verify the mixed signal chip design. But after that I started work
on the calibration process, for the purpose of providing customers with a ‘gold
standard’ calibration process to copy. The calibration process involves measuring
the RF TX & RX chains, and recording measurements on the device, mainly for the
purpose of guaranteeing TX power and RX RSSI. I am constantly looking for ways
to improve the calibration speed, for cost reduction purposes. I was involved in
specifying the AT command set used for calibration and debugging, as well as
writing all the calibration functions. I also specified how the RF driver makes use
of the calibration parameters.
The calibration program was included into a suite of programs, mostly written by
me. The programs performed various tasks:
Flashing firmware onto devices
Manual control of the RF & baseband
Tracking the history of devices
Attaching and making calls
Temperature and supply characterisation
Validation against 3GPP (not written by me)
Types of measurements/calculations performed in calibration:
AGC characteristics, ACLR, IQ DC offset, TX & RX ripple, Bezier smoothing/interpolation.
More recently, I have been involved in creating and simulating algorithms for use
within the device firmware for various purposes including: Xtal control, dynamic PA voltage
control, Class-S PA design. Lately, I have spent some time modifying RF driver code to
reduce the load on the RF driver team. In doing this I had to quickly get familiar
with this form of embedded C programming.
Dates: Feb. 1995 – May2005.
Company: Zarlink Semiconductor, Swindon, Wiltshire.
Domain: Bipolar semiconductor design and manufacture.
Position: Test Development Engineer (permanent).
Details: This position involved the development of RF test fixtures for communications
semiconductors. Test fixtures came under two categories - design evaluation and
final test. I was involved in several versions of a 'Cartesian feedback' circuit, which
operates at 2GHz. I was fully involved in most aspects of the chip design,
interacting with the designers and giving performance feedback. The bench
evaluation system was written in Agilent Vee, and the program 'front end' I wrote
was adopted by many other engineers. I also developed software for final testing of
this complex device on a Teradyne 'Catalyst' test machine.
I also worked on some complicated baseband devices, as well as other RF transmit
devices. On these devices I was heavily involved in the bench evaluation.
Types of measurements performed:
IP3/5, IIP3/5, ACPR, CSO & CTB, IQ phase & amplitude accuracy, Differential phase & gain, INL & DNL,
PLL measurements, Phase noise, narrowband noise, wideband noise, Filter characteristics using NW analyser,
Mixer-related tests – suppression of unwanted signals, Propagation delay, Group delay, (EVM investigated, not
performed), Rise/fall times, BER (@ 2.5 Gbit/s), ‘GPS’ trim methodology, S-parameters (for matching), Laser
diode characteristics, Sinad, THD, Prescaler response detection.
I wrote three data analysis packages using Excel VBA:
* DAT – takes input from the Vee ‘front-end’ (VFE) for design evaluation
& bench characterisation.
* Crunch – takes input from stdf datalogs, for high volume temperature &
supply characterisation of batches, against the data sheet limits.

3. * Firm-n-Crunchy takes input from stdf datalogs (and VFE), for
production monitoring of statistics, with wafermapping. This replaced the
old Teradyne ‘Firms’ package we used to use.
As appreciation for my work and for my potential, my manager sent me on a 1 year
'Professional Development Programme', in which I learned about many aspects of
business.
Dates: Sept. 1990 - Feb. 1995
Company: CorinTech, Fordingbridge, Hampshire.
Domain: Thick film Hybrid / SM PCB design and manufacture.
Position: Senior Engineer (permanent).
Details: I assisted with the running of all the processes of thick-film design, prototyping and
production. Although test interface design was initially the bulk of my work, I
became proficient at hybrid and SM PCB design using Vutrax.
My main responsibility involved writing build instructions and deputy management
i.e. making engineering and administrative decisions.
I was also involved at the quoting stage, where technical liaison with the customer
was required, as with aiding in circuit design, packaging solutions and testing and
AOT solutions.
Dates: Nov. 1989 - Sept. 1990
Company: Dowty Maritime, Greenford, Middlesex.
Domain: Sonar and Communications (Defence).
Position: Senior Test Systems Engineer (permanent).
Summary: RF, analogue and digital test fixture design.

4. Skill Summary
NVIDIA/Icera Semiconductor:
IEEE control (Agilent Vee expert)
CMU200, Ag8960 communication testers
Mobile datacard calibration
C++ (small involvement)
Embedded C programming
Zarlink Semiconductor:
RF design and measurement using network analysers and spectrum analysers
IEEE control (Agilent Vee expert)
Analogue circuit simulation & design (Electronics Workbench, Protel)
ATE software design (Teradyne 'Image')
Semiconductor fault analysis
PCB design and layout (Protel expert)
Test strategy design
Some management skills (Professional development program)
Excel VBA - creating data analysis packages
Corintech:
Deputy Management
Cad design of Thick Film hybrids, SM & conventional PCB's, test equipment and
tooling.
Test equipment - design and build
Faultfinding:
Product faults
Test equipment
Software debugging
PC based IEEE and user port control and related software
AOT and passive laser trimming of resistors
Thick film screen printing
Customer liaison
Dowty:
Design and procurement of auto test facilities using Fluke logic tester.
Analogue/digital circuit design for test purposes.
HP Basic IEEE control and programming.
Z80 code programming
RF test equipment design and commissioning (to 1.3 GHz)
Use of RF test equipment (HP network analysers, noise analysis equipment and
related equipment).
MIL STD 1553 interface use and understanding.
'Orcad' cad design.
Faultfinding:
RF
IEEE control test equipment
Product fault isolation
Factory Equipment
Additional Skills:
Analog/Audio/Power design
Logic design
Computer Programming (Pascal, 'C', BBC Basic, GW & Quick Basic).
Machine Code (6809, 6502, Z80)