Key points of Digital Predistortion (DPD) Technique for linearizing RF Power Amplifiers. Those work were done when I was in University College Dublin, Ireland.

1. High Performance Digital Predistortion
For Wideband RF Power Amplifiers
High Performance Digital Predistortion
For Wideband RF Power Amplifiers
From Concept to Implementation
Visit To CTVR, Trinity College Dublin, Ireland
Dr. Lei Guan
(lei.guan@ieee.org)
Visit To CTVR, Trinity College Dublin, Ireland

2. From Concept to Implementation
Verification
ConceptProblem
Digital
Scientific R&D Topic:
Specific;
Measurable;
Achievable;
Result-oriented;
Time-limited.
/1915th August 2012 2 Dr. Lei Guan
(lei.guan@ieee.org)
Simulation
System
Implementation
Digital
Predistortion
VHDL

3. Why need for Power Amplifier (PA) ?
Problem -> Concept -> System -> Simulation -> Implementation -> Verification
Mobile Network
Base station
/1915th August 2012 3
PA: analogue circuit, converting
DC power to added RF power
PA: analogue circuit, converting
DC power to added RF power
Mobile Network
TransceiverPower Amplifier
• Wireless communication: communicate
with anyone, at anywhere, at anytime;
• To perform long distance wireless
transmission, base stations are required
for communications signal relay;
• Power amplifiers are used to increase
the power of signal.
• Wireless communication: communicate
with anyone, at anywhere, at anytime;
• To perform long distance wireless
transmission, base stations are required
for communications signal relay;
• Power amplifiers are used to increase
the power of signal.
Dr. Lei Guan
(lei.guan@ieee.org)

4. Why need for Wideband PA ?
Problem -> Concept -> System -> Simulation -> Implementation -> Verification
/1915th August 2012 4
Wider bandwidth transceiver requiredWider bandwidth transceiver required
Higher data density modulation requiredHigher data density modulation required• To provide faster data transmission
(Video call, on-line movie… )
• To provide better service to more
users
• To provide faster data transmission
(Video call, on-line movie… )
• To provide better service to more
users
Dr. Lei Guan
(lei.guan@ieee.org)

5. Why need for High-efficiency PA ?
Typical PA efficiency: 15~30%Typical PA efficiency: 15~30%From Vodafone
PA
Problem -> Concept -> System -> Simulation -> Implementation -> Verification
/1915th August 2012 5
• Economic: reduce wasted cost to
save €€€€;
• Green ICT: reduce wasted power
consumption to save energy;
• Environmental: reduce CO2 to
save earth;
• Economic: reduce wasted cost to
save €€€€;
• Green ICT: reduce wasted power
consumption to save energy;
• Environmental: reduce CO2 to
save earth;
High-efficiency PA requiredHigh-efficiency PA requiredFrom NSN
Dr. Lei Guan
(lei.guan@ieee.org)

6. Linearity and Efficiency Compromise
Problem -> Concept -> System -> Simulation -> Implementation -> Verification
/1915th August 2012 6
PA
T-domain
F-domain
How to provide maximum PA
efficiency with satisfactory
linearity ?
How to provide maximum PA
efficiency with satisfactory
linearity ?
PA must be operated at linear
region !
PA must be operated at linear
region !
Dr. Lei Guan
(lei.guan@ieee.org)

7. Digital Predistortion (DPD)
Problem -> Concept -> System -> Simulation -> Implementation -> Verification
/1915th August 2012 7
• Extend linear operation region of power amplifiers
• Digital signal processing (Reliable and flexible)
• Standalone unit (Integrated and duplicable)
PA
Dr. Lei Guan
(lei.guan@ieee.org)

8. DPD System Requirement
• Digital Predistorter (DPD):
Problem -> Concept -> System -> Simulation -> Implementation -> Verification
/1915th August 2012 8
• Digital Predistorter (DPD):
– Accurate behavioral models required to describe inverse behavior;
– Real-time processing/High speed hardware implementation required.
• Parameter Extraction / Model Extraction:
– Coefficients value initialization/ adaptation;
– Can be “slowly” updated, not necessarily real-time.
• Data forward and feedback path:
– High speed ADC and DAC required;
– Up-converter and down-converter required.
Dr. Lei Guan
(lei.guan@ieee.org)

9. DPD Simulation System
Problem -> Concept -> System -> Simulation -> Implementation -> Verification
/1915th August 2012 9
• MATLAB/Simulink environment;
• To validate DPD idea/algorithm for genetic RF nonlinear system;
• Simplified system simulation, ideal DAC/ADC, Mod/Demod units;
• Rapid algorithm validation;
• Low cost and flexible;
• But not Physical test for PAs in real wireless systems.
Dr. Lei Guan
(lei.guan@ieee.org)

10. DPD Simulation Results
AM/AM
Problem -> Concept -> System -> Simulation -> Implementation -> Verification
Volterra model
Coefficients are linear with respect to input
/1915th August 2012 10
DPD model
extraction
PSD
LS/LMS
Linear System ID
Dr. Lei Guan
(lei.guan@ieee.org)

11. Direct DPD Implementation
Direct structure: A large number of
complex multipliers are required, and this
number increases dramatically when
nonlinear order P and memory length M
increase
Direct structure: A large number of
complex multipliers are required, and this
number increases dramatically when
nonlinear order P and memory length M
increase
1 1
2 2
2 2( 1) 2 *
2 1,1 2 1,2
0 0 1 1
( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
P P
M M
k k
k k
k i k i
u n g i x n x n i g i x n x n x n i
 

 
   
           Volterra model:
Problem -> Concept -> System -> Simulation -> Implementation -> Verification
/1915th August 2012 11
Hardware Multiplier (HM) occupies a large area of silicon; dedicated signal
processing units with limited number on chip, e.g., Xilinx Virtex-4 XC4SX35 (
Only 192 DSP48 units)
Hardware Multiplier (HM) occupies a large area of silicon; dedicated signal
processing units with limited number on chip, e.g., Xilinx Virtex-4 XC4SX35 (
Only 192 DSP48 units)
Dr. Lei Guan
(lei.guan@ieee.org)

12. Low-cost DPD Implementation
1. LUT-assisted Gain Indexing:
Memory is much cheaper than hardware multipliers
2. TDM-based Multiplier Sharing:
FPGA clock is faster than required data rate
Problem -> Concept -> System -> Simulation -> Implementation -> Verification
1 1
2 2
2 2( 1) 2 *
2 1,1 2 1,2
0 0 1 1
( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
P P
M M
k k
k k
k i k i
u n g i x n x n i g i x n x n x n i
 

 
   
           Volterra model:
/1915th August 2012 12
[L. Guan, WO 2010/136114 A1]
Dr. Lei Guan
(lei.guan@ieee.org)

13. DPD Validation Platform Design
Problem -> Concept -> System -> Simulation -> Implementation -> Verification
• Practicability: Focus on Fundamental units
• Flexibility: 2-Mode DPD (soft & Hard)
Hardware (e.g., FPGA) + Software (e.g., Matlab)
• Expandability: Design each function independently
• Practicability: Focus on Fundamental units
• Flexibility: 2-Mode DPD (soft & Hard)
Hardware (e.g., FPGA) + Software (e.g., Matlab)
• Expandability: Design each function independently
/1915th August 2012 13
[L. Guan, et al., EI project report]
Dr. Lei Guan
(lei.guan@ieee.org)

14. Matlab-based Graphic User Control Panel (PC)
Problem -> Concept -> System -> Simulation -> Implementation -> Verification
Other necessary functions are required
to get the whole system running
properly, as shown in the diagram
/1915th August 2012 14
Graphic User Control Panel Background Layer of Control Panel
Dr. Lei Guan
(lei.guan@ieee.org)

15. FPGA-based Core Logics (Baseband)
Clock Management
Logics (Multi -
region clocks)
Clock Management
Logics (Multi -
region clocks)
Data Interface
Logics (UART,
LVDS)
Data Interface
Logics (UART,
LVDS) Xilinx Virtex 5
Problem -> Concept -> System -> Simulation -> Implementation -> Verification
/1915th August 2012 15
User Defined
Logics (DPD,…)
User Defined
Logics (DPD,…)
External ICs
Configuration
Logic (DAC,…)
External ICs
Configuration
Logic (DAC,…)
Mode:
1. Soft-DPD
2. Hard-DPD
Mode:
1. Soft-DPD
2. Hard-DPD
Dr. Lei Guan
(lei.guan@ieee.org)

16. Typical Analog Front-end (RF)
Problem -> Concept -> System -> Simulation -> Implementation -> Verification
/1915th August 2012 16 Dr. Lei Guan
(lei.guan@ieee.org)

17. Picture of the DPD Test Platform
Problem -> Concept -> System -> Simulation -> Implementation -> Verification
Robust Validation
Procedure:
1. FPGA -> EXP ->
FPGA
(Chip Loop);
2. PC -> FPGA ->PC
(Digital Loop);
/1915th August 2012 17
3. ESG -> RF -> FPGA
-> PC (RX);
4. PC -> FPGA -> RF
->PSA (TX);
5. PC -> FPGA -> RF
-> FPGA -> PC
(System loop);
Step1: Physical link validation;
Step2: Core function validation;
Dr. Lei Guan
(lei.guan@ieee.org)

18. DPD Linearization Performance
Problem -> Concept -> System -> Simulation -> Implementation -> Verification
/1915th August 2012 18
PA: Doherty PA;
Fc: 2.14 GHz;
Sig: 8-carrier UMTS
(40 MHz);
ACPR (± 5MHz): (Required spectral mask: -45 dB)
W/O DPD -25 dB;
With DPD -57 dB;
EVM (%):
W/O DPD 10.77%;
With DPD 0.39%;
Dr. Lei Guan
(lei.guan@ieee.org)

19. Q and A
• Basic introduction of Digital Predistortion;
• Include all the fundamental development
procedure (From concept to implementation);
• Can be used to compensate for nonlinear
distortion in other electronic systems (ADC, Echo
/19
distortion in other electronic systems (ADC, Echo
cancellation…)
• Thanks for your attention !!
15th August 2012 19 Dr. Lei Guan
(lei.guan@ieee.org)