A low voltage radiation-hardened 13 t sram bitcell for ultralow

A Low-Voltage Radiation-Hardened 13T SRAM
Bitcell for Ultralow Power Space Application
Presented By
Ananth Mahadev
ERD18ECVE04
11/11/2018
A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications
1
Guided by:
Ms.Divya D S

Overview
 Introduction
 Objective
 Existing system
 Literature survey
Single-Event Upsets (SEUs)
Standard SRAM under SEUs
 Theory of 13T SRAM
 Proposed 13T Radiation Tolerant Bitcell
 Considerations in the Design
 Results
 Advantages and Limitations
 Conclusion
 References
11/11/2018
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Introduction
 What’s an SRAM(Static Random Access Memory)?
 The memory circuit is said to be static if the stored data can be retained
indefinitely, as long as the power supply is on, without any need for periodic
refresh operation.
 Volatile in nature
 3 Operation states:
Hold
Write
Read
11/11/2018A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications
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Fig.1 A Typical 6T SRAM Bitcell

Introduction(Cont’d)
 SRAM is used in electronic systems in Space Technology i.e. for
Satellite communications.
 As the need for viable units are increasing, high density and speed
requirements are to be improved for SRAM Bitcells
4
Fig.2 International Space Station

Objective:
 Here the solution for tackling the issue of Single Event Upsets(SEUs)
in SRAM cells used for space applications will be demonstrated.
The proposed radiation-hardened bitcell is a pioneer solution for
embedded memories in low-power space applications.
To Design a novel solution with high stability under varying
voltage and process parameter variations ,with an outstanding
advantage over the conventional 6T SRAM cell.
To achieve High-radiation tolerance under scaled supply voltages,
into the sub-threshold region are discussed.
5

Existing System:
 Higher Power consumption
 More prone to radiation
 Lower Durability of the system.
 Employs 6T Bitcells with limited range of operating voltages.
6

Literature Survey:
 Researches to implement an Ultra Low Power ,Robust and efficient
SRAM bitcell with High soft error tolerance and wide range of
operating voltage are conducted.(Ref [2])
The existing 6T SRAM bitcell doesn’t meet these expectations
completely
 This work put forth a novel 13T SRAM bitcell meeting the above
expectations(Ref. [1])
7

Literature Survey
Single-Event Upsets (SEUs):
 Soft errors or single-event upsets (SEUs) caused by radiation strikes
are the primary causes of failure in VLSI circuits operating within a
highly radiating environment.
 Soft errors occur when an energetic particle hits and passes through
a semiconductor material, potentially causing a bit ﬂip in the
memory cell.
 SEUs and other similar single-event effects (SEEs) are often
considered when designing for space applications and other high-
radiation environments.
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Single-Event Upsets (SEUs) cont’d:
 When the particle hits a reverse-biased p-n-junction, such as a
transistor diffusion-bulk junction:
 the injected charge is transported by drift and causes a transient
current pulse that changes the node voltage,
 Data loss occurs when the collected charge (Qcoll) exceeds the
critical charge (Qcrit) that is stored in the sensitive node.
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Standard SRAM under SEUs
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Fig.3 (a) Conventional 6T SRAM cell. (b) Example of an SRAM bit ﬂip caused by an SEU.

Theory of 13T SRAM:
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 The proposed bitcell is specially designed to enable robust, low-
voltage, ULP operation in space applications and other high-
radiation environment.
 This is achieved by employing a dual-feedback, separated-feedback
mechanism to overcome the increased vulnerability due to supply
voltage scaling.
 By driving the acute data level by a pair of equipotentially driven,
but independent, inverters, a strong, dual-driven feedback
mechanism is applied with node separation for SEU protection. This
setup eﬀectively protects Q from an upset, while achieving a high
critical charge at node Q.

Proposed 13T Radiation Tolerant Bitcell
Fig.4 Proposed 13T SRAM bitcell
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Proposed 13T Radiation Tolerant Bitcell cont’d:
Considerations in the design
 Proposed design was depicted in Fig.4
 The following steps are the path for designing the bitcell:
 Bitcell Design
 Storage Mechanism (Hold)(depicted in Fig.5)
 Inherent SEU Tolerance
The data are read out from node Q, such that any temporary upset on other
nodes can be tolerated.
The assisting nodes are designed with redundancy to ensure that any upset
will be mitigated by the other nodes.
 Write Operation(depicted in Fig.6)
 Read and Half Select.(depicted in Fig.7) 11/11/2018
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Fig.5 Storage states
Fig.6 Write operation

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Fig.7 Half-select functionality for both, storing 1 (cell 1) and storing 0 (cell 2), cases.

Result:
SEU Tolerance
 Disrupt Modeling
 The transient current I(t) due to radiation on a pn junction is given by equation
(1);
I(t) =
𝑄𝑐𝑜𝑙𝑙
𝑡𝑓−𝑡𝑟
𝑒
−
𝑡
𝑡𝑓 − 𝑒
−
𝑡
𝑡𝑟 - (1)
 where Qcoll is the charge collected due to the particle strike, tr is the rise time,
and tf is the fall time. Qcoll depends on the type of the ionizing particle,
trajectory, energy value, and impact location.
 Disrupt Tolerance (depicted in Fig.8)
 Recovery Time and Critical Charge(depicted in Fig.9)
16

Result: cont’d.
SEU Tolerance
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Fig.8 Subsequent write-upset-read events, demonstrating quick cell recovery. The waveforms
were plotted for a 500-mV supply voltage with the particle energies of 1 pC.

Result: cont’d.
SEU Tolerance
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Fig.9 Behavior of node Q under all possible SEUs with charge deposit of 500 fC
and VDD =500 mV. Insets: results of 1000 MC simulations.

Result: cont’d.
Layout Considerations
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Fig.10 Bitcell layout

Result: cont’d.
 Implemented Bitcell
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Fig.11 Full chip layout and the 13T cell memory array

Advantages and Limitations
 Advantages
Efficient and Ultra Low Power operation provides a stable and
reliable Space system.
Robust operation
High soft-error tolerance.
 Limitations
High area overhead
complex implementation
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Conclusion:
 Here a 13T SRAM bitcell, designed for robust, low-voltage, ULP
operation in high-radiation environments, such as those encountered
by space applications was presented .
 A novel, robust and ULP operating Bitcell was defined for space
applications.
 High soft error tolerance bitcell described.
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References:
 [1]Lior Atias, Robert Giterman, Student Member, IEEE, Adam Teman, Pascal
Meinerzhagen and Alexander Fish ,Member, IEEE. ”A Low-Voltage Radiation-
Hardened 13T SRAM Bitcell for Ultralow Power Space Applications”, IEEE
TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI)
SYSTEMS: REGULAR PAPERS,August-2016.
 [2] Adam Teman, A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback
SRAM (SFSRAM) in IEEE JOURNAL OF SOLID-STATE
CIRCUITS,VOL.46,NO.11,NOVEMBER 2011
 [3] Radiation Hardened Memories for Space Applications,Nadim F. Haddad,
Ronald D. Brown, Scott Doyle and Steven J. Wright BAE SYSTEMS 9300
Wellington Road, Manassas, VA 201 10 USA
 [4] Design Approaches for Radiation Hardening in Digital Circuits,Oliver
H¨oftberger,Institute of Computer Engineering Vienna University of Technology
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A low voltage radiation-hardened 13 t sram bitcell for ultralow

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