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io-esd

  1. 1. I/O & ESD Design Byron Krauter, IBM Mark McDermott
  2. 2. Outline  I/O Signaling Requirements  Basic CMOS I/O and Receiver Design  Real-world CMOS I/O and Receiver Design – Impedance Matching & Slew Rate Control – Mixed Voltages – ESD and other extreme conditions  Increasing Bandwidth – Source Synchronous I/O or Co-transmitted Clock – Pipelined Bus or Bus Pumping – Dual Data Rate – Simultaneous Bi-Directional – Pattern Based Driver Compensation  Transmission Lines08/28/12 2
  3. 3. I/O Signaling  There are basically two forms of signaling used for input/output applications – Single Ended – Differential  In single-ended signaling one wire carries a varying voltage that represents the signal, while the other wire is connected to a reference voltage, usually ground. – Single ended signaling is less expensive to implement than differential, but its main limitations are that it lacks the ability to reject noise caused by differences in ground voltage level between transmitting and receiving circuits.  Differential signaling uses two complementary signals sent on two separate wires. – Able to reject common-mode noise – More expensive to implement from both a wire perspective as well as the transmit & receive logic.08/28/12 3
  4. 4. Single Ended vs. Differential Signaling  Single Ended  Differential08/28/12 4
  5. 5. Single-ended Bus Signaling StandardsCourtesy Mike Morrow, UW08/28/12 5
  6. 6. Differential Bus Signaling StandardsCourtesy Mike Morrow, UW08/28/12 6
  7. 7. Complications  Pin Count Limitations – Bi-directional signaling – Simultaneous switching noise  Transmission Line Behavior – Limited net topologies work – Terminations required – Skin effect – Dielectric loss  Other Noises – Reflections – Discontinuity noise – Crosstalk and connector noise  Mixed Voltages  ESD and Other Handling Complications08/28/12 7
  8. 8. Basic CMOS I/O and Receiver Design
  9. 9. Bidirectional CMOS I/O Buffer enable_b Pad data enable 0 1 0 0 Hi Z data 1 1 Hi Z08/28/12 9
  10. 10. CMOS Input Receiver  Any two input gate that – Has good noise immunity – Provides on-chip control when off-chip inputs float  Example: two input NAND enable enable 0 1 Pad 0 1 1 data out data 1 1 0 X 1 X08/28/12 10
  11. 11. Real-world CMOS I/O Design
  12. 12. Real-world CMOS I/O Design  Output Impedance Control  Slew Rate Control  Mixed Voltage Designs – Input Design for Higher Voltages – Output Design for Higher Voltages • Dual Power Supplies • Floating Well Designs • Open Source Signaling  Other Circuits – Differential I/O Circuits – Hysteresis Receivers  ESD Circuits08/28/12 12
  13. 13. Output Impedance Control  Device “resistances” are too variable for source termination – Devices are non-linear – Variations due to VDD, Temp, and process variations alone are >2X in linear region!  Output stages must be designed to reduce this variation – On-chip resistors designs – Logically tunable designs08/28/12
  14. 14. Impedance Control Using On-Chip Resistors  Given a precise on-chip resistor, this design provides the best impedance control enable_b Pad data08/28/12 14
  15. 15. Tunable Impedance Control  Stacked device settings can be preset or dynamically controlled p1 p2 p3 enable_b Pad data n1 n2 n308/28/12 15
  16. 16. Slew Rate Control  Output stage slew rate is controlled to reduce noise – Cross talk noise – Simultaneous switching noise – Reflections at discontinuities  Slew rate control is accomplished by controlling the pre-driver delay and/or pre-driver strength08/28/12 16
  17. 17. Slew Rate Control  Output stage is divided and pre-drive signal is designed to sequentially arrive at the different sections δ δ enable_b Pad data δ δ08/28/12 17
  18. 18. Slew Rate Control & Impedance Control  Pre-driver design might even permit crossover currents to guarantee impedance even during switching δ δ enable_b Pad δ data δ δ δ08/28/12
  19. 19. Feedback Slew Rate Control I/O Bufferenable_b Pad data08/28/12 19
  20. 20. Feedback Slew Rate Control I/O Buffer (Patents)08/28/12 20
  21. 21. Mixed Voltage Designs  Needed when chips have different supply voltages  Low voltage circuits can be damaged by high voltage inputs  High voltage circuits suffer delay & noise problems when receiving low voltage signals VDD_1 Bi-directional VDD_2 I/O Buffers newer older technology technology VDD_1 < VDD_208/28/12
  22. 22. Input Design for Higher Voltages  Modifications for gate oxide & ESD protection Receiving Same Level Receiving Higher Level ESD Diodes ESD Diodes Pad Pad change beta ratio08/28/12
  23. 23. Dual Supply Designs  Separately power I/O circuits at a lower voltage – No additional process steps required – Extra design to avoid performance penalty – ESD & simultaneous switching noise compromised VDD_1 Bi-directional VDD_1 VDD_2 I/O Buffers newer older technology technology08/28/12
  24. 24. Output Stage at a Lower Voltage  Slow rising delay due to low overdrive on PMOS  Reduced drive = reduced noise immunity on NAND receiver Vdd2 Vdd1 Vdd1 or Vdd2 ESD Diodes enable_b Pad data inhibit08/28/12 24
  25. 25. Output Stage at a Lower Voltage  Improve rising delay with NMOS pull up  Change p/n beta ratio on NAND to lower switch point 1.8 Volts 1.2 Volts 1.2 or 1.8 Volts ESD Diodes enable_b Pad data Inhibit_b change beta ratio08/28/12 25
  26. 26. Dual Supply Designs  Separately power the I/O circuits at a higher voltage – More complicated circuits – ESD & simultaneous switching noise compromised 1.2 Volts 1.8 Volts Bi-directional 1.8 Volts I/O Buffers newer older technology technology08/28/12 26
  27. 27. Output Stage at a Higher Voltage  Slow rising delay due to low overdrive on PMOS  Reduced drive = reduced noise immunity on NAND receiver Vdd2 Level Vdd2 Shifter Vdd1 enable_b Vbias Pad data Vdd108/28/12
  28. 28. Floating Well Designs  Enabled output stage outputs a lower voltage -> Vdd1  Disabled output stage tolerates higher voltage -> Vdd2 Vdd1 Vdd1 enable Vdd1 Pad data Vdd108/28/12
  29. 29. Open Drain Signaling  Avoids complexity of multiple chip power supplies – Off-chip termination resistors pull net up – On-chip NMOS devices pull net down  Increases transmission line design complexity  Wired OR functionality Driving Chip Vtt Vtt CL CL CL CL CL08/28/12 29
  30. 30. Other Circuits  Differential I/O Circuits – Reduces simultaneous switching noise – Improves receiver common mode noise immunity – Receives smaller signal levels – “Pseudo” to full differential possible  Hysteresis Receivers – High noise immunity – Excellent for low-speed asynchronous test & control signals  Hold Clamps08/28/12 30
  31. 31. Differential Output Buffers Pseudo Differential Outputs out Differential Outputs out VDD out out Vbias08/28/12 31
  32. 32. 32 08/28/12 Differential = coupled pair Zeff < Zo coupled Zeff < Zo Pseudo = two lines Zo Zo Differential Transmission Lines
  33. 33. Differential Far End Termination Pseudo Differential Termination R = Zo Rtt = Zo V Vtt Differential Termination R = 2 Zo08/28/12 33
  34. 34. Differential Receivers Pseudo Differential Receiver out Differential Receiver out VDD out out Vbias08/28/12 34
  35. 35. Self Biased Differential Receiver  Combines best of NMOS and PMOS differential receivers VDD Pbias VDD out out out out Nbias08/28/12 35
  36. 36. Self Biased Differential Receiver  Combines best of NMOS and PMOS differential receivers – Rail to rail output swing – Excellent common mode noise rejection VDD out or reference (Bazes, JSSC 91)08/28/12 36
  37. 37. Hysteresis Input Receivers  Separates rising & fall edge dc transfer curves weak feedback inverter Pad Vin Vout inhibitPad Vin Vout falling rising Vout AND only Vin08/28/12 37
  38. 38. Hold Clamps  Weak clamps hold tri-stated source terminated nets weak feedback inverter Pad VDD I/O  Stronger clamps will actively terminate the net – Can be slower than passive termination schemes08/28/12 38
  39. 39. ESD Design  Pins subjected to ESD (electrostatic discharge) events during test & handling  Over-voltages can also occur during functional operation – System power-on – Hot-plugging  ESD discharge can occur between any two pins – I/O to I/O – I/O to VDD or Gnd  Pins are measured against standard ESD tests – Human body model – Machine model – Charged Device Model  ESD performance depends on many parameters other circuits don’t care about08/28/12 39
  40. 40. ESD Circuits  Non-breakdown based circuits – Diodes – Bipolar Junction Transistor – MOSFET  Breakdown based circuits – Thick Field Oxide Device – SCR (silicon controlled rectifier)08/28/12
  41. 41. Dual Diode ESD Circuits Single Supply Design Mixed voltage design ESD Diodes ESD Diodes Pad Pad08/28/12 41
  42. 42. FET ESD Circuits: non-breakdown mode NMOS in “diode” configuration ESD Diodes Pad08/28/12 42
  43. 43. FET ESD Circuits: breakdown mode ESD Diodes Pad second breakdow n I snapback NMOS protects Vgs > Vt by clamping voltage after device snapback V08/28/12 43
  44. 44. Diode ESD Circuits  FET devices are parasitic npn & pnp bipolar circuits • vertical pnp device to substrate • horizontal npn device to guard rings (before trench isolation) • low vdd to gnd impedance to due on-chip capacitance provide additional discharge paths ESD Diodes ESD bipolar devices Pad Pad08/28/12 44
  45. 45. Parasitic Bipolar Circuits  FET devices are parasitic npn & pnp bipolar circuits • vertical pnp device to substrate08/28/12
  46. 46. ESD Test Models  Human Body Model – Requirements 2 - 4 kVolts – Positive or negative discharge between any two pins R = 1.5 KΩ VHBM DUT C = 100 pF ipeak = VHBM/1500 i(t) t = 2-10 nsec time08/28/12
  47. 47. ESD Test Models  Machine Model – Requirements 200 - 400 Volts – Positive or negative discharge between any two pins L = 0.5 - 0.75 µH VMM DUT R < 8.5 Ω C = 200 pF08/28/12
  48. 48. ESD Performance Factors  Diode symmetry is important – Bipolar conduction increases with temperature – Hot spots conduct more, heat up more, conduct more, … and finally burn out  Layout corners are rounded to reduce electric fields  Decoupling capacitance needed between all supplies  Functional performance requirements impose ESD size & load capacitance constraints  Parasitic bipolar effects abound  Breakdown clamps don’t scale  Virtual supply node needed for multi-VDD designs08/28/12
  49. 49. Increasing Bandwidth08/28/12
  50. 50. Common Clock Transfers  Chip to chip transfers controlled by common bus clock  Equal length card routes to each chip & on-chip PLL’s minimize clock skew Chip A PLL PLL Chip B clock source08/28/12 50
  51. 51. Common Clock Transfers Cycle time to meet setup time max(Tclk - A+TAclk +Tdrive+ Ttof+ Treceive + Tsetup ) - min(TBclk - Tclk - B) < Tcycle Chip A Tdrive Ttof Treceive Tsetup TBclk TAclk PLL PLL Chip B Tclk - A Tclk - B clock source08/28/12 51
  52. 52. Source Synchronous I/O  Send source clock with source data  Resolve clock phase differences with τ 1, τ 2, & τ 3 Chip B Chip A τ3 τ1 τ2 PLL PLL clock source08/28/12 52
  53. 53. Bus Pumping  With Ttof > Tcycle, multiple bits are present on the wire Chip A Chip B τ3 τ1 τ2 PLL PLL clock source08/28/12 53
  54. 54. Dual Data Rate  Conventional source synchronous design – Data launched & captured on single clock edge – Clock switches at f – Maximium data rate = 1/2 * f  Dual data rate - if clock can switch at f, why not data? – Data is launched & captured on both clock edges – Clock switches f – Maximum data rate = f Conventional Dual Data Rate Clock Data08/28/12 54
  55. 55. Simultaneous Bidirectional Signaling  Two chips send & receive data simultaneously on a point to point net  Waveforms superimpose on the transmission line  Each chip selects it’s receiver reference voltage based on the data it sent  Sending data is subtracted from total waveform Chip A Chip B 3/4 VDD 3/4 VDD 1/4 VDD 1/4 VDD08/28/12 55
  56. 56. Pattern Based Driver Compensation  Incident waveforms along a long-lossy lines attenuate  Slow “RC” like response to final level Rs = Zo Vs τf where τ f = length / velocity With complex impedance and propagation constant high speed wavefront decays exponentially 1/2 (1- e-R*length/2Zo)08/28/12 56
  57. 57. Pattern Based Driver Compensation  Adjust driver strength based on bits sent in earlier cycles  Example: When driving low to high – Drive harder if previous bits sent = 00 – Drive weaker if previous bits sent = 10 Drive harder Receiver Switch Point 1 0 0 0 0 1 Without Compensation 1 0 0 0 0 1 With Compensation08/28/12 57
  58. 58. Increasing Bandwidth  Preceding techniques cannot be achieved through clever circuit design alone  Requires good packaging technology & net design – Good termination – Minimal capacitive & inductive discontinuities – Low cross-talk – Low simultaneous switching noise08/28/12 58
  59. 59. Backup
  60. 60. Transmission Line Behavior
  61. 61. But First A Few Words onCommon Ground Interconnect Models
  62. 62. Example - Two Wires & One Source  Twin lead transmission line modeled as a single section and driven by a Thevenin source Rsource L11 Rwire 0.5*Cwire M12 0.5*Cwire L22 Rwire08/28/12 62
  63. 63. Example - Two Wires & One Source  Being concerned with local potentials only (i.e. capacitor potentials) inductances and resistances can be combined Rsource L11 Rwire L22 Rwire 0.5*Cwire M12 0.5*Cwire Rsource L11+ L22 - 2*M12 0.5*Cwire 2*Rwire 0.5*Cwire08/28/12 63
  64. 64. Example - Three Wires & Two Sources  When multiple wires form a cutset, treat one wire as a reference lead and fold it into the other wires*. Rs1 L11 R1 Cutse t 0.5*C1g M1g 0.5*C1g Rg 0.5*C12 0.5*C12 M12 Lgg 0.5*C2g M2g 0.5*C2g Rs2 L22 R2 * Brian Young, “Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages”08/28/12 64
  65. 65. Example - Three Wires & Two Sources  Resulting loop impedance model for three parallel wires driven by two Thevenin sources mutual resistances Rs1 L11+Lgg-2M1g R1+Rg v1 i2Rg 0.5*C1g 0.5*C1g M12-M1g-M2g+Lgg 0.5*C12 v2 0.5*C12 i1Rg Rs2 L22+Lgg-2M1g R2+Rg 0.5*C2g 0.5*C1g08/28/12 65
  66. 66. Transmission Line Behavior  On and off chip signals can always be modeled with lumped RLC circuits  Wire segments are modeled with π or t segments  L, R, C, and G can be frequency dependent  But inductance is not always important08/28/12 66
  67. 67. Transmission Line Behavior  Inductance is important when – Driver source impedance R is low s Rs < Z o where Zo = characteristic impedance of line – Driver rise time τ is fast r τ r < 2.5 τ f Wave front where τ f = time of flight decays exponentially with this constant – Line loss is low R << jωL or (R / 2Zo) << 1  Can be restated for point to point nets as08/28/12 RsCtot < 1/2 RlineCline < τ f 67
  68. 68. When Inductance is Important  Nets ring and net delays become unpredictable unless: – Net topologies are constrained • Point to point nets • Periodically loaded nets • Near and far end clusters – Nets are driven appropriately • Not to strong and not to weak • Not to fast and not to slow – Nets are terminated appropriately • Source termination • Far end termination – Resistance to VDD or Gnd or any Thevenin Voltage • AC termination = RC circuit • Active hold clamps • Diode or Schottky diode clamps08/28/12 68
  69. 69. Transmission Line Behavior  Perfectly source terminated point to point, loss-less net Rs = Zo τf L Zo = C τ f = LC far end V(t) near end τf time08/28/12 69
  70. 70. Transmission Line Behavior  Under driven point to point, loss-less net Rs = 3Zo τf L Zo = C τ f = LC Approximates far end RC step response V(t) near end time08/28/12 70
  71. 71. Transmission Line Behavior  Over driven point to point, loss-less net Rs = 1/3 Zo τf L Zo = C τ f = LC far end V(t) near end time08/28/12 71
  72. 72. Reflection and Transmission With incident wave Vinc traveling down the line Voltage reflection coefficient { ZL - Zo 1, ZL= ∞ Γv = Γv = 0, ZL= Zo ZL+ Zo -1, ZL= 0 Voltage transmission coefficient 2ZL Τv = 1 + Γv = ZL+ Zo08/28/12 72
  73. 73. Equivalent Circuits Along Line Rs near end + Vs Zo Vinc - Zo along line 2Vinc Zo Zdiscontinuity Zo far end 2Vinc ZL08/28/12 73
  74. 74. Discontinuities Along Line Rs = Zo Vs=1 1 Vs C 1/2 1/2 (1- e-2t/ZoC) Vs=1 Rs = Zo 1 1/2 Vs L 1- 1/2(1- e-2Zot/L)08/28/12 74
  75. 75. Well Behaved Net Topologies  Point to Point Nets Source terminated Rs = Zo τf Far end terminated Rs << Zo τf Vterm Rterm ≅ Zo08/28/12
  76. 76. Well Behaved Net Topologies  Periodically Loaded Nets Source terminated: Near end switches last Rs = Zeff CL CL CL CL L Zeff = C + nCL With periodic loading τf = L(C+nCL)08/28/12
  77. 77. Well Behaved Net Topologies  Periodically Loaded Nets Far end terminated: Near end switches first Rs << Zeff Rterm ≅ Zeff Vterm CL CL CL CL L Zeff = C + nCL With periodic loading τf = L(C+nCL)08/28/12
  78. 78. Well Behaved Net Topologies  Near end (or Star) cluster Rs = Zo/N08/28/12
  79. 79. Well Behaved Net Topologies  Far-end cluster Rs = Zo/N Zo/N08/28/12
  80. 80. Well Behaved Net Topologies  Double far-end terminated bus Rs << Zo Vterm Vterm CL CL CL CL CL08/28/12
  81. 81. Ideal Transmission Lines Ideal I(z) Telegrapher’s Equation ∂i ∂V = −C ∂z ∂t ∂ 2V ∂ 2V V(z) = LC 2 ∂V ∂i ∂z 2 ∂t = −L ∂z ∂t − j ( γz −ωt ) j (γz +ωt ) V = Re [V + e +V − e ] Steady State Solution: 1 + − j (γz −ωt ) j ( γz +ωt ) I = Re ( [V e +V e − ]) Z Z= L where C γ =ω LC08/28/12 81
  82. 82. Transmission Lines with Loss jωL + R j γ (ω) = (jωL + R) jωC Z(ω) = jωC ≅ L ≅ jω LC (1 - j R/2ω L) (1 - j R/2ω L) C R R Z (ω ) = Z 0 − j γ (ω ) = ω LC + 2ω C Z0 2 Z008/28/12 82
  83. 83. Waveforms Along a Low Loss Line Rs << Zo Vs τf where τ f = length / velocity With complex impedance & complex propagation constant high speed wavefront decays exponentially & distorts 1 (1- e-R*length/2Zo)08/28/12 83
  84. 84. Distortionless Transmission Line Oliver Heaviside (1887) G/C = R/ L jωL + R j γ (ω) = (jωL + R)(jωC + G) Z(ω) = jωC + G L = LC ( jω + R /L) = C08/28/12 84
  85. 85. Waveforms Along a Distortionless Line Rs << Zo Vs τf where τ f = length / velocity With real impedance and complex propagation constant high speed wavefront decays exponentially but without distortion 1 (1- e-R*length/Zo)08/28/12 85

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