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Serial Io

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Serial Io

  1. 1. SERIAL I/O WITH 8085<br />
  2. 2. Basics of serial communication<br />
  3. 3. SERIAL I/0 MODE<br />DEVICE<br />MODEM<br />(SERIAL)<br />PROCESSOR<br />(PARALLEL)<br />PARALLEL TO SERIAL<br />SERIAL TO PARALLEL<br />
  4. 4.
  5. 5. SYNCHRONOUS TRANSMISSION<br />CLK<br />TRANSMITTER<br />RECEIVER<br />SYNC<br />SYNC<br />DATA<br />
  6. 6. ASYNCHRONOUS TRANSMISSIONStart and stop bits<br />
  7. 7. SYNCHRONOUS <br /><ul><li> BLOCK OF DATA TRANSMITTED ALONG WITH SYNC INFORMATION
  8. 8. HIGH SPEED TRANSMISSION</li></ul>ASYNCHRONOUS<br /><ul><li>CHARACTER CARRIES INFORMATION WITH START AND STOP BITS
  9. 9. WHEN NO DATA IS TRANSMITTED RECEIVER STAYS AT LOGIC 1 CALLED MARK ; LOGIC 0 CALLED SPACE
  10. 10. TRANSMISSION STARTS WITH ONE START BIT AND ONE OR MORE STOP BITS . THIS IS FRAMING</li></li></ul><li>Serial Interfaces: RS-232<br /><ul><li>DB25S is a 25 pin connector with</li></ul>full RS-232 functionality<br /><ul><li>The computer socket has a female</li></ul>outer casing with male connecting<br />pins<br /><ul><li>The terminating cable connector</li></ul>has a male outer casing with<br />female connecting pins<br />
  11. 11. TTL to RS-232<br />
  12. 12. Types of equipment<br />DTE Data Terminal Equipment<br /><ul><li>Originally applied to CRT terminals or other input devices
  13. 13. Today, DTE mainly applies to a computer</li></ul>DCE Data Communication Equipment<br /><ul><li>Originally applied to modems or similar communications</li></ul>equipment<br /><ul><li> Still applies today</li></ul> A modem is a device that converts a digital signal (e.g. from<br />an RS232 interface) to an analogue signal for transmission<br />over a traditional telephone line (MODEM: MOdulator-<br />DEModulator)<br />
  14. 14. VOLTAGE LEVEL <br />+3V TO +15 V<br />LOGIC 0<br />VOLTAGE LEVEL <br />-3V TO -15 V<br />LOGIC 1<br />YEP…. THATS RIGHT…..<br />HERE WE USE<br />NEGATIVE TRUE LOGIC<br />BUT USUSALLY <br />LOGIC 1  +12V<br />LOGIC 0-12V<br />????!!!!!!<br />
  15. 15. <ul><li> TO MAKE RS 232 COMPATIBLE WITH TTL LOGIC ,
  16. 16. VOLTAGE TRANSLATORS CALLED LINE DRIVERS & LINE RECEIVERS ARE USED</li></li></ul><li>RS232 pins<br />
  17. 17. SIGNALS OF RS232<br />
  18. 18. We are concerned about,<br />
  19. 19.
  20. 20.
  21. 21.
  22. 22. <ul><li>11 bits required to send a single character (10 if one stop bits are used)
  23. 23. Bit rate (bits/sec): actual rate at which bits are transmitted
  24. 24. Baud rate: rate at which the signalling elements, used to represent bits, are transmitted</li></li></ul><li>DTE Vs DCE<br />DCE<br /> MODEM<br />DTE<br />MICRO<br />COMPUTER<br />TX<br />RX<br />2<br />2<br />TX<br />RX<br />3<br />3<br />GND<br />7<br />7<br />
  25. 25. DTE Vs DTE<br />DTE<br />DTE<br />TX<br />TX<br />2<br />2<br />RX<br />RX<br />3<br />3<br />GND<br />7<br />7<br />*NULL MODEM CONNECTION<br />
  26. 26. Typical System Connections<br />7<br />7<br />
  27. 27. SERIAL INTERFACES : 8251A USART<br /> The functions and requirement for SERIAL I/O are,<br /><ul><li>Input port & Output port for interfacing
  28. 28. DATA TX MPU converts parallel to serial
  29. 29. DATA RX  MPU converts serial to parallel
  30. 30. Synchronization between MPU and slow peripheral</li></ul>USART – Universal Synchronous /Asynchronous Receiver/ Transmitter<br /> It incorporates all the above features in a single chip and other sophisticated functions for serial communication.<br /> It is a programmable device i.e its functions and specifications for serial i/o can be determined by writing instructions to its internal registers<br />8251A USART  device widely used for serial i/o<br />
  31. 31. The 8251A Programmable Communication Interface<br />8251A<br />
  32. 32. 8251A- BLOCK DIAGRAM<br />
  33. 33.
  34. 34. 8251A- PIN DIAGRAM<br />
  35. 35.
  36. 36. READ/WRITE CONTROL LOGIC AND REGISTERS<br />SIX INPUT SIGNALS<br />THREE BUFFER REGISTERS<br /><ul><li> STATUS REG.
  37. 37. CONTROL REG
  38. 38. DATA REG.</li></ul>INPUT SIGNALS<br /><ul><li>CS’ – CHIP SELECT
  39. 39. LOGIC 0 8251 is selected by the MPU
  40. 40. RD’ – READ SIGNAL
  41. 41. LOGIC 0  The MPU reads the status from status register or accepts input from data buffer
  42. 42. WR’ – WRITE SIGNAL
  43. 43. LOGIC 0 The MPU writes in the control register or sends data to output buffer </li></li></ul><li><ul><li>C/D’– CONTROL / DATA
  44. 44. LOGIC 0 data buffer is addressed
  45. 45. LOGIC 1  control register or status register is addressed
  46. 46. CONTROL REGISTER - ->WR’</li></ul> STATUS REGISTER -- &gt; RD’<br /><ul><li>RESET – Reset
  47. 47. LOGIC 1  forces 8251 to RESET and enters into idle mode
  48. 48. CLK - clock
  49. 49. REFERS TO SYSTEM CLOCK
  50. 50. Necessary for communication with the processor</li></li></ul><li>
  51. 51. REGISTERS<br /><ul><li>CONTROL REGISTER
  52. 52. 16 BIT REGISTER
  53. 53. first byte  MODE INSTRUCTION ( WORD )
  54. 54. second byte  COMMAND INSTRUCTION ( WORD )
  55. 55. Register can be accessed when C/D’ is HIGH and WR’ is LOW
  56. 56. STATUS REGISTER
  57. 57. Input register that checks the READY status of the peripheral
  58. 58. Register can be accessed when C/D’ is HIGH and RD’ is LOW
  59. 59. DATA REGISTER
  60. 60. 8 BIT bidirectional register – addressed as input or output
  61. 61. Register can be accessed when C/D’ is LOW</li></li></ul><li>TRANSMITTER SECTION<br /> TRANSMITTER - CONVERTS PARALLEL FROM MPU TO SERIAL<br /> TWO REGISTERS – BUFFER REGISTER – TO HOLD 8 BITS - OUTPUT REGISTER – TO CONVERT TO STREAM OF SERIAL BITS<br />THREE OUTPUT AND ONE INPUT SIGNALS<br />INPUT SIGNAL :<br /> TXC’ - TRANSMITTER CLOCK<br />CONTROLS THE RATE AT WHICH BITS ARE TRANSMITTED BY USART<br />CLOCK FREQ – 1/16/64 TIMES THE BAUD<br />
  62. 62. OUTPUT SIGNAL :<br />TXD - TRANSMIT DATA<br /> SERIAL BITS ARE TRANSMITTED ON THIS LINE<br />TxRDY – TRANSMITTER READY<br /> LOGIC 1 – BUFFER EMPTY; USART READY TO ACCEPT<br /> TO INTERRUPT MPU or INDICATE STATUS<br />TxE – TRANSMITTER EMPTY<br /> LOGIC 1 – OUTPUT REGISTER IS EMPTY<br /> LOGIC 0 - BYTE IS TRANSFERRED FROM BUFFER TO REG.<br />
  63. 63. RECEIVER SECTION<br /> RECEIVER - CONVERTS SERIAL TO PARALLEL<br /> TWO REGISTERS - INPUT REGISTER – TO HOLD SERIAL 8 BITS WITH START & STOP BITS AND CONVERT THEM TO PARALLEL - BUFFER REGISTER – TO STORE PARALLEL BITS<br />TWO INPUT AND ONE OUTPUT SIGNALS<br />INPUT SIGNAL :<br /> RXC’ - RECEIVER CLOCK<br />CONTROLS THE RATE AT WHICH BITS ARE RECEIVED BY USART<br />CLOCK FREQ – 1/16/64 TIMES THE BAUD<br />
  64. 64. RXD - RECEIVE DATA<br /> SERIAL BITS ARE RECEIVED ON THIS LINE<br />OUTPUT SIGNAL :<br />RxRDY – RECEIVER READY<br /> LOGIC 1 – USART HAS A CHARACTER IN THE BUFFER REGISTER NAD READY TO TRANSFER TO MPU<br /> TO INTERRUPT MPU or INDICATE STATUS<br />
  65. 65. 7<br />6<br />5<br />4<br />3<br />2<br />1<br />0<br />Mode register<br />Number of <br />Stop bits<br />Baud Rate<br />00: Syn. Mode<br />01: ASYNC x1 <br />10: ASYNC x16 <br />11: ASYNC x64 <br />00: invalid<br />01: 1 bit<br />10: 1.5 bits<br />11: 2 bits<br />Character length<br />00: 5 bits<br />01: 6 bits<br />10: 7 bits<br />11: 8 bits<br /> 8251 mode register- MODE WORD<br />PARITY CONTROL<br />X0 – NO PARITY<br />01 – ODD PARITY<br />11 – EVEN PARITY<br />
  66. 66. Command Register<br />
  67. 67. Status Register<br />
  68. 68. INITIALISING THE 8251A<br /> MPU INFORMS 8251 – MODE, BAUD, STOP BITS, PARITY<br /> CONTROL WORDS TO BE LOADED FROM MPU TO 8251<br />
  69. 69. OPERATION FLOW<br />

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