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Get it right the first time lpddr4 validation and compliance test

JEDEC LPDDR4 Compliance and Validation Testing. Learn about electrical and protocol testing and validation. DDR Memory is in almost all computing devices today.

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JEDEC Mobile
& IOT Forum
Copyright © 2016 FuturePlus Systems
Get it right the first time!
How to test for compliance to the
LPDDR4 JEDEC Specification
Barbara Aichinger
Vice President
FuturePlus Systems Corporation
Represented in China by Fullwise Technologies
LPDDR4 Specification
• The JEDEC LPDDR4
Specification is a DRAM
specification
• There is no specification
for the memory controller
– Which is what you need to
test!
• There is no LPDDR4
Compliance Specification
Don’t Worry! Help is
on the way!
What to test on your LPDDR4 design?
• That the LPDDR4 DRAM is being
treated properly
– Electrical
• Signal Integrity on all signals
• Receiver Eye size
• BER – Bit Error Rate
– Protocol
• Protocol Checks
• Power up /power down states
• Performance
LPDDR4 Command/Address Rx
Mask
• Do you know the
difference
between the
‘Mask’ and the
Data Valid Eye?
Mask: The area (voltage and time)
where no signal may encroach in order
for the DRAM to successfully capture
Rx Data Valid Eye: Is the voltage/time
opening measured at the receiver
DQ Data Rx Mask
6
Measuring System
Compliance
6
Vcent (one for all
DQs, one for all CAs)
Mask center time
calculated separately for
each signal
About 1E6 bits
accumulated by
scope at DRAM pin
Dual-dirac eye extra-
polation to (TBD) BER
(approx. 1E-9 to 1E-16)
Extrapolated eye must
not touch the mask
Ad

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Get it right the first time lpddr4 validation and compliance test

  • 1. JEDEC Mobile & IOT Forum Copyright © 2016 FuturePlus Systems Get it right the first time! How to test for compliance to the LPDDR4 JEDEC Specification Barbara Aichinger Vice President FuturePlus Systems Corporation Represented in China by Fullwise Technologies
  • 2. LPDDR4 Specification • The JEDEC LPDDR4 Specification is a DRAM specification • There is no specification for the memory controller – Which is what you need to test! • There is no LPDDR4 Compliance Specification Don’t Worry! Help is on the way!
  • 3. What to test on your LPDDR4 design? • That the LPDDR4 DRAM is being treated properly – Electrical • Signal Integrity on all signals • Receiver Eye size • BER – Bit Error Rate – Protocol • Protocol Checks • Power up /power down states • Performance
  • 4. LPDDR4 Command/Address Rx Mask • Do you know the difference between the ‘Mask’ and the Data Valid Eye? Mask: The area (voltage and time) where no signal may encroach in order for the DRAM to successfully capture Rx Data Valid Eye: Is the voltage/time opening measured at the receiver
  • 5. DQ Data Rx Mask
  • 6. 6 Measuring System Compliance 6 Vcent (one for all DQs, one for all CAs) Mask center time calculated separately for each signal About 1E6 bits accumulated by scope at DRAM pin Dual-dirac eye extra- polation to (TBD) BER (approx. 1E-9 to 1E-16) Extrapolated eye must not touch the mask
  • 7. LPDDR4 Bus Level Signal Integrity Insight • A quick way to get bus level signal integrity insight is to use a logic analyzer – With high speed ‘scanning’ capabilities • All signals can be observed and compared to each other • Signals with problems can be identified quickly – An oscilloscope then used on the problem signals
  • 8. 8 Signal Integrity Insight: Cross Talk on ADDRESS January 2014 Eye Scan Insight: Crosstalk on ADDR 8 and ADDR9 Symptom: Random intermittent data corruption on DDR4 system Next Steps: •Check routing for crosstalk threats. (missing ground planes, traces too close to each other or to noise source….) Slide Courtesy of
  • 9. 9 Signal Integrity Insight: LPDDR4 DQS Clean DQS strobes on BGA interposer for both Read/Write 3 Gb/s Read strobe (DQS0) probed single ended. 3 Gb/s Write strobe (DQS0) probed single ended. Slide Courtesy of
  • 10. 10 Signal Integrity Insight: DDR4 3500 Mb/s Read Scans Next Steps: • Take trace to inspect ODT operation • Cross trigger scope to check for ISI Eye Scan Insight: •Potential ODT setting issue. Threshold of first bit in burst has less swing than remainder of burst. •Could also be ISI (inter-symbol interference) • Overdriving DDR4 DRAM to 1.4V could cause damage. Slide Courtesy of
  • 11. 11 Signal Integrity Insight: Incorrect Signal Transition Eye Scan Insight Symptom: Data Corruption on DDR4 system Next Steps: • SW work around: – Do not use BG1 = 1 – Limits address space • Long term: HW fix required DDR4 Bank Group 1 Transitioning incorrectly Slide Courtesy of
  • 12. Looking for Protocol Violations • What is a Protocol violation? – The specification has rules about: • How close in time transactions can be to each other – Example:Time between an ACTIVATE and a Read or Write can be no closer than tRCD • How far apart transactions can be from each other – Example:Time between two REFRESH commands cannot be greater than 9*tREFImax • The ordering of transactions – Example: A Read or Write command must be preceded with an ACTIVATE command to the selected ROW
  • 13. 13 Example: Protocol Violation Average Refresh Rate When the Refresh rate falls below the 100% bar (indicating too few Refresh): • Red dots indicate the locations • Too few Refresh = risk of data corruption
  • 14. Example: Protocol Violation Write to close to a PREA Last cycle of a 4 cycle Write Command Time between equals WL+BL/2+tWR+1 8 +32/2+ 15 + 1 = 40 clocks Measurement is 38 clocks: VIOLATION PREA closes the bank. If this happens too quickly then the data may not be written properly
  • 15. Example: Protocol Violation tRCD ACTIVATE to close to a Read tRCDmin = MAX(tRCD{nCK}, ROUNDUP((tRCD{ns}/tCK{ns})-0.025)) 24 clocks 4 ((18ns/.625ns)-0.025) 29 3200MT/s
  • 16. LPDDR4 Violation Spreadsheet Made available by FuturePlus Systems
  • 17. Probing • BGA interposer – Flying lead – Midbus – Cable connection • Midbus • Slot Interposer
  • 18. Probing LPDDR4 using a BGA interposer with individual probe points Riser DRAM BGA Interposer DRAM Motherboard Probe Point DRAM BGA Interposer Grounds Signals Photos Courtesy of
  • 19. BGA probing with a scope
  • 20. BGA Probing with a Protocol Analyzer Photos courtesy of
  • 22. Probing LPDDR4 using a midbus footprint
  • 23. Probing LPDDR4 Using a BGA interposer with a cable connection to a Protocol Analyzer or Logic Analyzer
  • 24. LPDDR4 Package on Package (PoP) Probing
  • 25. LPDDR4 on a SODIMM • Some applications looking at this – No ECC • Will use the same form factor as DDR4 SODIMM • Slot interposer can be used for probing
  • 26. Equipment Logic analyzer Oscilloscope Protocol Analyzer Photos courtesy of Keysight Technologies and FuturePlus Systems
  • 27. Summary for Success • Put a robust validation and compliance plan in place for your product • One that verifies the electrical and the protocol operation • Plan your probing ahead of time so you can achieve success easily!
  • 28. Contact Information Barbara Aichinger Vice President FuturePlus Systems Corporation 15 Constitution Drive Bedford NH 03110 USA Barb.Aichinger@FuturePlus.com USA 603-472-5905 www.FuturePlus.com www.DDRDetective.com Represented in China by Full Wise Technology www.FullWiseTech.com