Digital Design Technology and Techniques. The class notes present basic digital logic design abstraction, electronic design process, and CAD tools for digital design.
Intze Overhead Water Tank Design by Working Stress - IS Method.pdf
SKEL 4273 CAD with HDL Topic 1
1. SKEL 4273: CAD with HDL
Ab Al-Hadi Ab Rahman, PhD
Semester 2017/2018-2
Universiti Teknologi Malaysia
Topic 1: Digital Design
Technology and Techniques
2. Outline
• Digital Logic Technologies
• Design Abstraction
• Electronic Design Process
• CAD Tools
3. Integrated Circuits
• IC chip consists of complex electronic circuitries
and their interconnections.
• W. Shockley et al of Bell Laboratories invented
the transistor in 1948.
• IC’s built with MOSFET transistors, i.e. CMOS
technology.
• Commercially available in 1960s.
• Phenomenal advancement in IC design and
fabrication technologies.
4. Integrated Circuits (cont.)
• More and more transistors are packed in a
chip – SSI, MSI, LSI, and VLSI.
• Intel 4004: > 8k transistors (1971)
• Intel i7: > 1.4 billion transistors (2015)
5. Integrated Circuits (cont.)
• Moore’s Law – maximum number of transistors on a
chip approximately doubles every eighteen months
• Has been accurate for the last 4 decades
6. Digital Design Implementation
• Various implementation of digital logic designs.
• Traditional off-the-shelf IC chips perform fixed
operation defined by the device manufacturer.
• Application Specific Integrated Circuits (ASICs) are
customized IC’s whose internal functional
operation is user-defined.
• CPLD or FPGA require user hardware
programming to perform the desired operation.
• The circuit-level design of a VLSI or ASIC chip
involves circuit components design, placement,
and interconnect routing.
7. Digital Design Implementation
Disadvantages
•Time consuming, especially full custom
•Semi-custom, automation available (costly)
•Requires full knowledge at circuit level
•Very long lead time
Advantages
•Flexibility in physical design
•Best in terms of power and performance
Disadvantages
•Less flexible at physical level
•Poor power consumption compared to
ASICs
•Much slower compared to ASICs
Advantages
•Allows quick design prototyping
•No fabrication, no lead time
Digital Design
ASIC FPGA
8. Digital Design Abstraction
• Today’s circuit are complex.
• Time-to-market is one of the more crucial
factors.
• Large scale design needs new design methods.
• Digital designers use two methods:
– Design abstraction
– Hierarchical modular design
• Need electronic design automation (EDA) or
computer aided design (CAD) tools.
9. Digital Design Abstraction (cont.)
• At each design level, internal details of a complex
module may be abstracted away and replaced by
a black box view or model.
• The model contains virtually all the information
needed to deal with the block at the next (lower)
level of the design hierarchy.
• No need for system designer to look inside the
box, design complexity is substantially reduced.
• Hardware designers use these multiple levels of
design abstraction to meet performance goals for
very large designs and reduce lead times.
11. Hierarchical Design Methods
• Divide and conquer approach for complex designs.
• Complex designs broken down into hierarchy of
modules.
• Benefits:
– Focus on a single module at a time
– Create customized low-level modules for design reuse
• Top down approach: decompose systems into smaller
subsystems to a level where the subsystems can be
realized.
• Bottom up approach: connects available modules to
form bigger, more complex subsystems.
15. Computer Aided Design (CAD)
• Makes design process efficient, timely,
economical.
• CAD tools are intended to support all phases of a
digital design
– Description (specification).
– Design (synthesis), including various optimizations to
reduce cost and improve performance.
– Verification (by simulation or formal approach) with
respect to its specification.
• These three phases typically require several
passes to obtain a suitable implementation.
16. Hardware Description Languages
• Replacing schematic capture.
• Today, VHDL and Verilog are the two widely
used languages.
• System Verilog also widely used nowadays
(not covered in our syllabus).
• We will use Verilog exclusively in this course.
• The description can coexist.
17. Schematic vs HDL
• Schematic capture at low abstraction level – traditional
way.
• Alternative is using HDL
– Reduced development time and allows more exploration
of design alternatives
– Description in high level of abstraction
– A mean to standardize method of specifying design
• Current trend is to specify systems at high-level using
block diagrams – increased design productivity
– C to HDL
– Matlab to HDL
– Domain specific languages (e.g. dataflow actors) to HDL
18. CAD Methodology
• Design entry in HDL (Altera Quartus II, Xilinx
Vivado, Mentor HDL Designer).
• HDL simulations - behavioural, functional,
timing (Modelsim, Vivado Simulator, VCS).
• Synthesis (Altera Quartus II, Xilinx Vivado,
Leonardo Spectrum).
• Implementation – converting netlist file to a
physical design to the target implementation
technology.
21. Tools for this course
• Xilinx Vivado – please download yourself
https://www.xilinx.com/support/download.html
• Recommended version 2016 – more stable and faster
interface.
• Latest version 2018 slightly heavy and could have some
bugs. However, it has better synthesis results.
• Comprehensively an integrated design environment
(IDE) for the design of digital systems
• Includes solutions for all phases of FPGA-based designs
• Simplifies management and design of complex SoCs
with SW and HW components, IP, etc.
• Supports C to HDL synthesis
