Design challenges in physical design


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Design challenges in physical design

  1. 1. SeminarDesign challenges in Physical Design Shankardas Deepti Bharat CGB0911002 VSD531 M. Sc. [Engg.] in VLSI System Design Module Title: IC planning & Implementation Module Leader: Mr. Chandramohan P. M. S. Ramaiah School of Advanced Studies 1
  2. 2. AgendaIntroductionGeneral challenges faced in designAnalogDigitalMixedNode comparisons in detail3D challengesSummaryReference M. S. Ramaiah School of Advanced Studies 2
  3. 3. Introduction With each new process technology, the number of transistors per unit areadoubles The typical area of a chip has remained more or less the same. Designers use the extra real estate to add more functions—Bluetooth one year, Wi-Fi the next, streaming video after that, and so on. As a result, the layout data for a chip design also doubles with each new node. The main issues of VDSM high performance physical designs are current density and power distribution, synchronization, manufacturing variability, high- frequency and coupling noise. M. S. Ramaiah School of Advanced Studies 3
  4. 4. Design objectives & ChallengesDesigners main motive with respect to design:Design Objectives:– Power (dynamic/static)– Timing (frequency)– Area (cost/yield)– Yield (cost)Challenges:– Manufacturing technology– Leakage power– Interconnect delay– Congestion– Reliability Figure 1. Physical flow [1] M. S. Ramaiah School of Advanced Studies 4
  5. 5. Congestion Design is said to be congested if there more tracks to be routed than the available tracks Objective: Determine routes (tracks, layers, and vias) for each net Such that the total wire length is minimized. Be careful with routing critical nets and clock nets Figure 2. Routing congestion [1] M. S. Ramaiah School of Advanced Studies 5
  6. 6. IR drop•Resistance in power grid causes a reduced supply voltage at the deliverypoint•An IR drop from 1.7V to 1.6V is capable of producing delay variation of50% or more•IR drop can be minimized •by increasing the number of core power pads •by increasing the number of metal layers carrying the power •by making the top metal layer extra thick for increased conductivity •by increasing the width of the power rails •by increasing the # of straps•IR drops leads to performance drop, signal integrity problems & electromigration Figure 3. IR drop analysis [3] M. S. Ramaiah School of Advanced Studies 6
  7. 7. Approach for power distribution Strapping and rings for  Using Power ringstandard cell Figure 4. Power distribution [2] M. S. Ramaiah School of Advanced Studies 7
  8. 8. Signal integrity •Ability of an electrical signal to carry information reliably & resist the effects of high frequency interference from nearby signals . •Conditions that can impact signal integrity are crosstalk &electromigration. Crosstalk Electromigration Figure 5. Crosstalk & electromigration [2] M. S. Ramaiah School of Advanced Studies 8
  9. 9. Challenges in Digital Design Chip assembly predictability• Physical Design Integration• Mixed-Signal Systems• Verification• Routing• Continuous Regression Simulation Chip integration speed and accuracy• Floorplanning and Optimization• Physical Verification• Physical Design Integration Rapid migration to a new process technology M. S. Ramaiah School of Advanced Studies 9
  10. 10. Challenges in Analog Design •Analog design often requires a very different variety of technology features, model accuracy, and integration sensitivities than digital design •Sensitivity to parasitics and overall modeling accuracy is much higherfor an analog design compared to digital design •Modeling of noise coupling is a critical need in analog design, and requires the extraction of substrate and well characteristics not typically required in most digital designs •The most problematical requirement of analog integration is the need for power-supply voltages which are at different potentials and/or electrically isolated from digital power supplies M. S. Ramaiah School of Advanced Studies 10
  11. 11. Challenges in Mixed Design•Analog circuits has to follow digital process which limits the analog circuitperformances•Design methodology/tools for reliability•Complex Interaction Between Analog and Digital blocks•MS involve signal paths crossing the interface between digital and analogblocks•Parasitic Coupling•Power dissipation constraints•Hot carrier injection•Reuse of IP’s•Testing•RF to a mixed-signal chip adds considerable risk•Model accuracy, and design methodology/tools for reliability M. S. Ramaiah School of Advanced Studies 11
  12. 12. Comparison of NodesLP devices do not follow HP scalingtrends. LP devices provide highervalues of Tox Radios, sensors, I/O, controllers, power management—all require The total number of design or provide interfaces to or rules has doubled between from variable power and 90 and 28nm, and rule signal sources. complexity is outpacing that for both LEF rules and the built-in DRC checkers provided with custom design tools Full-featured DRC/DFM engines offer a variety of techniques and information to assist designers during debugging and design optimization Difference in emphasis also affects the roles people play in the design process. Figure 6. Nodes comparison [5] M. S. Ramaiah School of Advanced Studies 12
  13. 13. Challenges in 3D designThermal issues (power density)• Consideration of active regions• Heat conduction (thermal vias)High design complexity•Additional degree of freedom (3rd dimension)•Vertical constraints•Efficient data structures and algorithmsTestability/Reliability/Yield/Costs•Redundant through silicon vias•Conduct integrated test structures outsideReuse of existing (2D) IP blocksBlockage area for TSVs Figure 7. 3D design challenges [6] and [7] M. S. Ramaiah School of Advanced Studies 13
  14. 14. 3D design challenges Research is also required to investigate the impact of TSV location •Pseudo 3D tools & their limitations on 3D IC design quality and reliability Possible solutions include tradeoff •Existing tools are used as a 3D extension studies between regular and non- regular TSV placement with respect to •Capable of handling simple 3D design wherein existingthese metrics 2D designs are stacked & connected without any major design change •This is done with the help of TSVs which deliver signal, power & clock in vertical directions •TSV management, How many & where?Mainly due to the large TSV size, •wirelength begins to increase as the TSVs have significant impact on the The count and location ofTSV count goes beyond this quality and reliability of 3D IC layoutsoptimum point. The number ofTSVs used in factor layout entirely • Cost 3D ICdepends on how the design ispartitioned into multiple dies. Figure 8. 3D design challenges [6] M. S. Ramaiah School of Advanced Studies 14
  15. 15. 3D design challengesThe 3D clock tree itself is the longest wire in Cooling solutions have beenthe circuit and contains many buffers to controlskew and slew. Since the delay characteristics proposed, including carbon nano-tube •Thermal managementof clock wires, buffers, and TSVs are based and liquid cooling with micro-significantly affected by the temperature, care scale fluidic channels (MFC) directly •Dies are stacked,must be taken to ensure that the skew is kept several hotspots are created which increase the 3D ICs inserted intominimum based on a given non-uniformthermal profile. background temperature the •Dummy TSVs are inserted to alleviate thermal problems Less congestion ,IR •May negatively impact area & manufacturability drop •Other cooling solutions such as carbon nano tube based and liquid cooling have been proposed •Clock delivery •Clock TSVs, as in the case with signal and P/G TSVs, occupy layout space and cause coupling •High thermal variations in 3D ICs induce a substantial amount of skew variation in the clock tree, which has adverse implications for the performance and reliability of 3D IC Figure 9. 3D design challenges [6] M. S. Ramaiah School of Advanced Studies 15
  16. 16. 3D design challenges Possible solutions include TSV-aware CMP fill synthesis for the top and bottom metal •TSVs induced design manufacturing issues layers, TSV stress-aware timing analysis and physical design and TSV-aware substrate •TSVs in 3D IC layouts cause significantlyand device reliability modelling and non-uniform layout density optimization. distributions on the active, poly, and M1 layers •Density variation issue is expected to cause trouble during CMP steps and requires new TSV-aware solutions Thermal management in the interposer itself is another important reliability issue that• Interposer-Based 3D Integration must be investigated.•Interposers today are typically made of silicon or glass and provide several layers ofmetal and vias for fine-pitch electrical connection among the dies that are surface-mounted .• 3D IC/interposer co-design methodology is crucial, where physical design for thissystem like P/G network synthesis and analysis are conducted in both levelssimultaneously with collaborative methods. Figure 10. 3D design challenges [6] M. S. Ramaiah School of Advanced Studies 16
  17. 17. Summary •Each successive advancement of semiconductor technology a new VDSM challenge is born. •For high performance reliable designs the industry has to face a wide variety of phenomenon such as heat dissipation, electro migration, interconnectcoupling & more. •Nevertheless in many cases of high performance designs current EDAtechnology does not have the full power to provide the best solution. •In 3D ICs, TSVs have been widely used for thermal management, power & clock delivery. •Accurate electrical, mechanical, and thermal modeling of TSVs is essentialin successful physical design of TSV-based 3D Ics. M. S. Ramaiah School of Advanced Studies 17
  18. 18. References[1] T. R. Bednar et al., ‘Issues and strategies for physical design of SOC ASICs’ , IBM Journal of Research and Development, 46 (6) , November 2002[2] Chunh-Wei Lin et al., ‘Recent Research & Emerging Challenges in Physical Design forManufacturability /Reliability’, [white paper] available at <> Retrieved on 01 Apr 2012[3] Dr. Danny Rittman, Challenges & Solutions in Physical Design for High-performance IC Design inVery-Deep-Sub- Micron (VDSM) Era, Jan 2004[4] Joe Davis (2011) ‘The challenge of analog, mixed-signal and custom physical implementation at28nm’, [online] available at <>Retrieved on 01 Apr 2012[5] Robert Fischbach, Jens Lienig, Tilo Meister, 3D Physical Design: Challenges and Solutions Instituteof Electromechanical and Electronic Design, Dresden University of Technology, Dresden, October 12,2011[6] Sung Kyu Lim, ‘TSV-Aware 3D Physical Design Tool Needs for Faster Mainstream Acceptance of3D ICs’, [online] available at < .com.pdf> Retrieved on01 Apr 2012 M. S. Ramaiah School of Advanced Studies 18
  19. 19. Thank YouM. S. Ramaiah School of Advanced Studies 19
  20. 20. RemarksSl. No. Topic Max. marks Marks obtained 1 Quality of slides 5 2 Clarity of subject 5 3 Presentation 5 4 Effort and question handling 5 Total 20 M. S. Ramaiah School of Advanced Studies 20