1. Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-1
LECTURE 300 – LOW VOLTAGE OP AMPS
LECTURE ORGANIZATION
Outline
• Introduction
• Low voltage input stages
• Low voltage gain stages
• Low voltage bias circuits
• Low voltage op amps
• Summary
CMOS Analog Circuit Design, 2nd Edition Reference
Pages 415-432
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-2
INTRODUCTION
Implications of Low-Voltage, Strong-Inversion Operation
• Reduced power supply means decreased dynamic range
• Nonlinearity will increase because the transistor is working close to VDS(sat)
• Large values of because the transistor is working close to VDS(sat)
• Increased drain-bulk and source-bulk capacitances because they are less reverse
biased.
• Large values of currents and W/L ratios to get high transconductance
• Small values of currents and large values of W/L will give smallVDS(sat)
• Severely reduced input common mode range
• Switches will require charge pumps
CMOS Analog Circuit Design © P.E. Allen - 2010

2. Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-3
What are the Limits of Power Supply?
The limit comes when there is no signal range left when the dc drops are subtracted from
VDD.
Minimum power supply (no signal swing range):
VDD(min.) = VT + 2VON
For differential amplifiers, the minimum power
supply is:
VDD(min.) = 3VON
However, to have any input common mode range, the
effective minimum power supply is,
VDD(min.) = VT + 2VON
+
VON
−
+
VT+VON
−
060802-01
VDD
VPB1
M2 M3
VT+VON
VNB1
M1
M4
+
−
+
VON
−
VON
M3 M4
M1 M2
VON +
VT+VON
060802-02
VPB1
VDD
+
VT+VON
−
VNB1
+
−
+
−
VON
−
+
−
M5
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-4
Minimum Power Supply Limit – Continued
The previous consideration of the differential amplifier did not consider getting the signal
out of the amplifier. This will add another VON.
+
−
VON
VT
M7 M8
M9
060802-03
VPB1
VDD
M3 M4
M1 M2
+
VT+VON
−
VNB1
+
VON +
−
+
VON
−
VON
−
+
−
VPB2
M6
VT+VON
M5
VPB1
+
−
VT+VON
Therefore,
VDD(min.) = VT + 3VON
This could be reduced to 3VON with the floating battery but its implementation probably
requires more than 3VON of power supply.
Note the output signal swing is VT + VON while the input common range is VON.
CMOS Analog Circuit Design © P.E. Allen - 2010

3. Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-5
LOW VOLTAGE INPUT STAGES
Input Common Mode Voltage Range
Minimum power supply (ICMR = 0):
VDD(min) = VSD3(sat)-VT1+VGS1+VDS5(sat)
= VSD3(sat)+VDS1(sat)+VDS5(sat)
Input common-mode range:
Vicm(upper) = VDD - VSD3(sat) + VT1
Vicm(lower) = VDS5(sat) + VGS1
If the threshold magnitudes are 0.7V, VDD =
1.5V and the saturation voltages are 0.3V, then
Vicm(upper) = 1.5 - 0.3 + 0.7 = 1.9V
and
Vicm(lower) = 0.3 + 1.0 = 1.3V
giving an ICMR of 0.6V.
VDD
M3 M4
VSD3(sat)
-VT1
vicm M1 M2
M5
VGS1
VDS5(sat)
+
-
VBias
+
-
VBias
Fig. 7.6-3
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-6
Increasing ICMR using Parallel Input Stages
Turn-on voltage for the n-channel input:
Vonn = VDSN5(sat) + VGSN1
Turn-on voltage for the p-channel input:
Vonp = VDD - VSDP5(sat) - VSGP1
The sum of Vonn and Vonp equals the minimum
power supply.
Regions of operation:
VDD
MN3 MP5
Vicm Vicm
MP1 MP2
MN1 MN2
MP3
MP4
MN4
MN5
IBias
M6
M7
Fig. 7.6-4
VDD Vicm Vonp: (n-channel on and p-channel off) gm(eq) = gmN
Vonp Vicm Vonn: (n-channel on and p-channel on) gm(eq) = gmN + gmP
Vonn Vicm 0 : (n-channel off and p-channel on) gm(eq) = gmP
where gm(eq) is the equivalent input transconductance of the above input stage, gmN is
the input transconductance for the n-channel input and gmP is the input trans-conductance
for the p-channel input.
gm(eff)
gmN+gmP
gmP gmN
n-channel off Vonn n-channel on Vonp
n-channel on
p-channel on p-channel on p-channel off
0 VSDP5(sat)+VGSN1 VDD-VSDP5(sat)+VGSN1 VDD
Vicm
Fig. 7.6-5
CMOS Analog Circuit Design © P.E. Allen - 2010

4. Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-7
Removing the Nonlinearity in Transconductances as a Function of ICMR
Increase the bias current in the differential
amplifier that is on when the other
differential amplifier is off.
Three regions of operation depending on the
value of Vicm:
1.) Vicm Vonn: n-channel diff. amp. off
and p-channel on with Ip = 4Ib:
gm(eff) =
KP’WP
LP
2 Ib
2.) Vonn Vicm Vonp: both on with
In = Ip = Ib:
gm(eff) =
KN’WN
LN
Ib +
Inn
Ip
Vicm Vicm
VB2 VB1
KP’WP
LP
MB2 MB1
Ib
VDD
Ib
MP1 MP2
Ib
1:3
MN1
In
3.) Vicm Vonp: p-channel diff. amp. off and n-channel on with In = 4Ib:
gm(eff) =
KN’WN
LN
2 Ib
3:1
MN2
Ipp
Fig. 7.6-6
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-8
How Does the Current Compensation Work?
Set VB1 = Vonn and VB2 = Vonp.
If vicm Vonp then Ip = Ib and Inn=0
If vicm Vonp then Ip = 0 and Inn=Ib
Vonn
vicm vicm
MN1 MN2
MB1
In Ipp
Ib
If vicm Vonn then In = Ib and Ipp=0
If vicm Vonn then In = 0 and Ipp=Ib
VDD
Vonp
Ib
Inn Ip
MP1 MP2
vicm vicm
MB2
Fig. 7.6-6A
Result:
gm(eff)
gmN=gmP
0 Vicm
Vonn Vonp VDD
0
Fig. 7.6-7
The above techniques and many similar ones are good for power supply values down to
about 1.5V. Below that, different techniques must be used or the technology must be
modified (natural devices).
CMOS Analog Circuit Design © P.E. Allen - 2010

5. Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-9
Natural Transistors
Natural or native NMOS transistors normally have a threshold voltage around 0.1V
before the threshold is increased by increasing the p concentration in the channel.
If these transistors are characterized, then they provide a means of achieving low voltage
operation.
Minimum power supply (ICMR = 0):
VDD(min) = 3VON
Input common mode range:
Vicm(upper) = VDD – VON + VT(natural)
Vicm(lower) = 2VON + VT(natural)
If VT(natural) VON = 0.1V, then
Vicm(upper) = VDD
Vicm(lower) = 3VON = 0.3V
Therefore,
ICMR = VDD - 3VON = VDD – 0.3V VDD(min) 1V
Matching tends to be better (less doping and magnitude is smaller).
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-10
Bulk-Driven MOSFET
A depletion device would permit large ICMR even with very small power supply voltages
because VGS is zero or negative.
When a MOSFET is driven from the bulk with the gate held constant, it acts like a
depletion transistor.
Cross-section of an n-channel
bulk-driven MOSFET:
Large signal equation:
iD =
KN’W
2L
vBS VDS VGS VDD
Bulk Drain Gate Source Substrate
p+ n+
Channel
p-well
Depletion
Region
n substrate
VGS-VT0- 2|F|-vBS+ 2|F| 2
Small-signal transconductance:
gmbs =
(2KN’W/L)ID
2 2|F|-VBS
n+
n+
QP
QV
Fig. 7.6-8
CMOS Analog Circuit Design © P.E. Allen - 2010

6. Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-11
Bulk-Driven MOSFET - Continued
Transconductance characteristics:
Saturation: VDS VBS – VP gives,
VBS = VP + VON
iD = IDSS
VBS
VP
1-
2
2000
1500
1000
500
Drain Current (μA)
IDSS
Bulk-source driven
Gate-source
driven
Comments:
0
• gm (bulk) gm(gate) if VBS 0
-3 -2 -1 0 1 2 3
Gate-Source or Bulk-Source Voltage (Volts)
(forward biased )
• Noise of both configurations are the same (any differences comes from the gate versus
bulk noise)
• Bulk-driven MOSFET tends to be more linear at lower currents than the gate-driven
MOSFET
• Very useful for generation of IDSS floating current sources.
Fig. 7.6-9
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-12
Bulk-Driven, n-channel Differential Amplifier
What is the ICMR?
Vicm(min) = VSS + VDS5(sat) + VBS1 = VSS + VDS5(sat) - |VP1| + VDS1(sat)
Note that Vicm can be less than VSS if |VP1| VDS5(sat) + VDS1(sat)
Vicm(max) = ?
As Vicm increases, the current through
M1 and M2 is constant so the source
increases. However, the gate voltage stays
constant so that VGS1 decreases. Since the
current must remain constant through M1
and M2 because of M5, the bulk-source
voltage becomes less negative causing VTN1
to decrease and maintain the currents
through M1 and M2 constant. If Vicm is
increased sufficiently, the bulk-source
voltage will become positive. However,
current does not start to flow until VBS is
greater than 0.3 volts so the effective
Vicm(max) is
M7
vi1 vi2
+
VBS1 -
+
VGS -
M6 M5
IBias
Vicm(max) VDD - VSD3(sat) - VDS1(sat) + VBS1.
VDD
M3 M4
VBS2 -
M1 M2
VSS
+
Fig. 7.6-10
CMOS Analog Circuit Design © P.E. Allen - 2010

7. Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-13
Illustration of the ICMR of the Bulk-Driven, Differential Amplifier
250nA
200nA
150nA
100nA
50nA
0
-50nA
Bulk-Source Current
-0.50V -0.25V 0.00V 0.25V 0.50V
Input Common-Mode Voltage
Fig. 7.6-10A
Comments:
• Effective ICMR is from VSS to VDD -0.3V
• The transconductance of the input stage can vary as much as 100% over the ICMR
which makes it very difficult to compensate
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-14
Reduction of VT through Forward Biasing the Bulk-Source
The bulk can be used to reduce the threshold sufficiently to permit low voltage
applications. The key is to control the amount of forward bias of the bulk-source.
Current-Driven Bulk Technique†:
S
D
IBB
G
B
S
D
IBB
G
B
IE
ICD ICS
Reduced Threshold MOSFET Parasitic BJT
Gate
Source Drain
n+
n-well
p+ p+
p- substrate
Layout Fig. 7.6-19
Problem:
Want to limit the BJT current to some value called, Imax.
Therefore,
IBB =
Imax
CS+CD+1
† T. Lehmann and M. Cassia, “1V Power Supply CMOS Cascode Amplifier,” IEEE J. of Solid-State Circuits, Vol. 36, No. 7, 2001.
CMOS Analog Circuit Design © P.E. Allen - 2010

8. Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-15
Current-Driven Bulk Technique
Bias circuit for keeping the Imax defined
independent of BJT betas.
Note:
ID,C = ICD + ID
IS,E = ID + IE + IR
The circuit feedback causes a bulk bias
current IBB and hence a bias voltage VBIAS
such that
IS,E = ID + IBB(1+CS + CD) + IR
M3
VDD
M1 M2
M7
R
IBB
IS,E
ID,C
M5 M4
M6
VBias1
M8
VBias2
+
VBias
IR
-
Use VBias1 and VBias2 to set ID,C 1.1ID,
IS,E 1.3ID and IR 0.1ID which sets IBB at 0.1ID assuming we can neglect ICS with
respect to ICD.
For this circuit to work, the following conditions must be satisfied:
VBE VTN + IRR and |VTP| + VDS(sat) VTN + IRR
If |VTP| VTN, then the level shifter IRR can be eliminated.
VSS
Fig. 7.6-20
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-16
LOW VOLTAGE GAIN STAGES
Cascade Stages
Simple cascade of inverters:
-gm4
R4
060803-01
VDD
VPB1
M2 M3
VNB1
M1
M4
VPB1
M5
M6
M7
VNB1
M8
-gm1
R1
-gm2
R2
-gm3
R3
The problem with this approach is the number of poles that occur (one per stage) if the
amplifier is to be used in a closed loop application.
CMOS Analog Circuit Design © P.E. Allen - 2010

9. Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-17
Nested Miller Compensation
Principle: Use Miller compensation
Cm3
to split the poles within a feedback
loop.
Cm2 Cm1
Compensating Results:
1) Cm1 pushes p4 to higher
vin
frequencies and p3 down to lower
frequencies
2) Cm2 pushes p2 to higher
frequencies and p1 down to lower frequencies
3) Cm3 pushes p3 to higher frequencies (feedback path) pulls p1 further to lower
frequencies
Equations:
p1 p2 p3 p4
v -g out -gm1 -gm2 m3 -gm4
060812-01
R1 R2 R3 RL CL
GB gm1/C m3 p2 gm2/Cm3 p3 gm3Cm3/(Cm1Cm2) p4 gm4/CL
The objective is to get all poles larger than GB:
GB p2, p3, p4
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-18
Illustration of the Nested Miller Compensation Technique
jω
σ
p4 p3 p2 p1
jω
σ
p4 p3 p2 p1
jω
σ
p4 p2 p3 p1
jω
σ
p4 p3 p2 p1
Cm1
Cm2
Cm3
-GB 070508-01
This approach is complicated by the feedforward paths which create RHP zeros.
CMOS Analog Circuit Design © P.E. Allen - 2010

10. Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-19
Elimination of the RHP Zeros
The following are least three ways in which the RHP zeros can be eliminated.
1.) Nulling resistor.
VPB1
Cc1
Rz1
060803-02
VDD
M2
M1
z1 =
1
Cc1(1/gm1Rz1)
2.) Feedback only – buffer.
Cc1
VPN1
VDD
060803-03
VDD
VPB1
M2
M1
M3
Increases the minimum power
supply by VON.
3.) Feedback only – gain.
VPB1
VDD
VPB2
VNB1
060803-04
VDD
Cc1
M2
M1
M3
M4
M5
Increases the pole and
increases the minimum
power supply by VON.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-20
Use of LHP Zeros to Compensate Cascaded Amplifiers
Principle: Feedforward around a noninverting stage creates a LHP zero or inverting
feedforward around an inverting stage also creates a LHP zero.
Example of Multipath, Nested Miller Compensation†:
CM1
CM2
Vin Vout
+gm1 +gm2
060803-05
R3
R1
+gm4
C3
-gm3
R2,4
M5 M6
VPB1
C CM1 M2
M1 M3 M4 M2
M8
VNB1
M7
VDD
M11
M9 M10
VRef1
M12
M14
M13
VRef2
Vout
C3
Vin
Unfortunately, the analysis becomes quite complex - for the details refer to the reference
below.
† R. Hogervorst and J. H. Huijsing, Design of Low-Voltage, Low-Power Operational Amplifier Cells, Kluwer Academic Publishers, 1996, pp. 127-131.
CMOS Analog Circuit Design © P.E. Allen - 2010

11. Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-21
Cascoding
Possibilities that trade off output resistance and headroom:
Rout
vout
M2
M1
Sat.
Act.
Gate-Connected Cascode
051205-01
VGG
ID
+
− v
Rout
out
No Cascoding
VT+2Von
VGG
ID
+
Rout
vout
−
M2
M1
Sat.
Sat.
Normal Cascoding
VT+2Von
VGG
ID
+
Rout
vout
−
M2
M1
Sat.
Act.
Reduced Headroom Cascoding
VGG
ID
+
−
No
Cascode
Normal
Cascode
Reduced Headroom
Cascode
Gate-Connected
Cascode
vout
Von1 1
1 +
ß1
ß2 1 +
ß1
ß2(2x-x2) 2x +
ß1
ß2(2x-x2)
Rout
rds 1 2ß2
2ID
2ß2(x-0.5x2)
ß1(1-x)+ ID x-0.5x2
2ß2(x-0.5x2)
ß1(1-x)+ ID x-0.5x2
Note: vDS(active) = x·Von1 = x·(VGG–VT)
x = 0.1 and ß2 = 9ß1 vout=1.145Von1 and Rout=1.45rds for reduced headroom cascode
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-22
Solutions to the Low Headroom Problem – High Voltage Tolerant Circuits
High voltage tolerant transistors in standard CMOS†:
VDD(nom.)
Upper gate
switched
to highest
potential
Thick oxide
transistor Thick oxide
050416-02
cascode
VDD(nom.)
Retractable cascode
composite transistor
(Transistor symbols with additional separation between the gate line and the channel line
represent thick oxide transistors.)
† Anne-Johan Annema, et. Al., “5.5-V I/O in a 2.5-V 0.25μm CMOS Technology,” IEEE J. of Solid-State Circuits, Vol. 36, No. 3, March 2001, pp.
528-538.
CMOS Analog Circuit Design © P.E. Allen - 2010

12. Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-23
LOW VOLTAGE BIAS CIRCUITS
A Low-Voltage Current Mirror with Wide Input and Output Swings
The current mirror below requires a power supply of VT+3VON and has a Vin(min) =
VON and a Vout(min) = 2VON (less for the regulated cascode output mirror).
I1-IB IB I2
iin
IB
M3
VDD
M4
M6
iout
M7
M1 M2
M5
or
iin
I1 IB2 IB1 I2
M1
M2
IB1
M3
VDD
M4
M6 M5
iout
M7
IB2
Fig. 7.6-13A
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-24
Low-Voltage Current Mirrors using the Bulk-Driven MOSFET
The biggest problem with current mirrors is the large minimum input voltage required for
previously examined current mirrors.
If the bulk-driven MOSFET is biased with a current that exceeds IDSS then it is
enhancement and can be used as a current mirror.
VDD
iin
iout
M1 M2
+
-
VGS
+
-
VBS
+
-
VGS
VDD
iin iout
M3 M4
+
-
VBS3
+
VGS4
-
M1 M2
+
VGS3
+
-
VGS1
-
+
-
VBS1
+
-
VGS2
Simple bulk-driven
current mirror
Cascodebulk-driven
current mirror. Fig.7.6-11
6 10-5
5 10-5
4 10-5
3 10-5
2 10-5
1 10-5
0
Cascode Current Mirror
All W/L's = 200μm/4μm
Iin=50μA
Iin=10μA
2μm CMOS
0 0.2 0.4 0.6 0.8 1
Iout (A)
Vout (V)
Iin=40μA
Iin=30μA
Iin=20μA
Fig. 7.6-12
The cascode current mirror gives a minimum input voltage of less than 0.5V for currents
less than 100μA
CMOS Analog Circuit Design © P.E. Allen - 2010

13. Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-25
Bandgap Topologies Compatible with Low Voltage Power Supply
VDD
VPTAT
VBE
IPTAT
VRef
Voltage-mode bandgap topology.
INL
IPTAT
VRef
VDD
IVBE
VDD
VDD
Current-mode bandgap topology.
IVBE
VRef
VDD
VDD VDD
IPTAT
INL
R2
R3
R1
Voltage-current mode bandgap topology
Fig. 7.6-14
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-26
Technique for Canceling the Bandgap Curvature
VDD
1:K2 1:K3
M1 M2 M3 M4
I2 INL
IVBE K1IPTAT
K3INL
Current
M2 active
M3 off
M2 sat.
M3 on
K2IVBE K1IPTAT
Temperature
INL
Circuit to generate nonlinear correction term, INL. Illustration of the various currents.
Fig. 7.6-16
INL =
0
K1IPTAT-K2IVBE
,
,
K2IVBEK1IPTAT
K2IVBEK1IPTAT
The combination of the above concept with the previous slide yielded a curvature-corrected
bandgap reference of 0.596V with a TC of 20ppm/C° from -15C° to 90C° using
a 1.1V power supply.† In addition, the line regulation was 408 ppm/V for 1.2VDD10V
and 2000 ppm/V for 1.1VDD10V. The quiescent current was 14μA.
† G.A. Rincon-Mora and P.E. Allen, “A 1.1-V Current-Mode and Piecewise-Linear Curvature-Corrected Bandgap Reference,” J. of Solid-State
Circuits, vol. 33, no. 10, October 1998, pp. 1551-1554.
CMOS Analog Circuit Design © P.E. Allen - 2010

14. Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-27
LOW VOLTAGE OP AMPS
A Low Voltage Op Amp using Normal Technology
VDD(min) = 3VON + VT (ICMR = VON):
M11
vOUT
Cc
M6 M7
M8 M9 M10
060804-01
VDD
VPB1
M3 M4
M1 M2
VNB1
VPB2
+
−
vIN
M5
Performance:
Gain gm2rds2
Miller compensated
Output swing is VDD -2VON
Max. CM input = VDD
Min. CM input = 2VON + VT
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-28
A Low-Voltage, Wide ICMR Op Amp
VDD(min) = 4VON + 2VT (ICMR = VDD):
3:1
+ −
1:3
041231-15
VDD
VDD-VT-VDS(sat)
VDD-VT-2VDS(sat)
VT+2VDS(sat)
VT+VDS(sat)
vOUT
Performance:
Gain gm2rds2, self compensated, and output swing is VDD -4VON
CMOS Analog Circuit Design © P.E. Allen - 2010

15. Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-29
An Alternate Low-Voltage, Wide ICMR Op Amp
VDD(min) = 4VON + 2VT (ICMR = VDD):
VDD
3:1
VPB2
VPB1
+ − vOUT
1:3
VNB2
060804-02
VPB2
VNB2
VNB1
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-30
A 1-Volt, Two-Stage Op Amp
Uses a bulk-driven differential input amplifier.
VDD=1V
6000/6 6000/6 3000/6 6000/6
M8 M9 M10 M11
vin+
vout
IBias
Cc=30pF
CL
Rz=1kΩ
vin-
2000/2
M1 M2
Q5 M3 M4 Q6
M12
M7
400/2 400/2 400/2
Fig. 7.6-18
CMOS Analog Circuit Design © P.E. Allen - 2010

16. Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-31
Performance of the 1-Volt, Two-Stage Op Amp
Specification (VDD=0.5V, VSS=-0.5V) Measured Performance (CL = 22pF)
DC open-loop gain 49dB (Vicm mid range)
Power supply current 300μA
Unity-gainbandwidth (GB) 1.3MHz (Vicm mid range)
Phase margin 57° (Vicm mid range)
Input offset voltage ±3mV
Input common mode voltage range -0.475V to 0.450V
Output swing -0.475V to 0.491V
Positive slew rate +0.7V/μsec
Negative slew rate -1.6V/μsec
THD, closed loop gain of -1V/V -60dB (0.75Vp-p, 1kHz sinewave)
-59dB (0.75Vp-p, 10kHz sinewave)
THD, closed loop gain of +1V/V -59dB (0.75Vp-p, 1kHz sinewave)
-57dB (0.75Vp-p, 10kHz sinewave)
Spectral noise voltage density 367nV/ Hz @ 1kHz
181nV/ Hz @ 10kHz,
81nV/ Hz @ 100kHz
444nV/ Hz @ 1MHz
Positive Power Supply Rejection 61dB at 10kHz, 55dB at 100kHz, 22dB at 1MHz
Negative Power Supply Rejection 45dB at 10kHz, 27dB at 100kHz, 5dB at 1MHz
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-32
A 1-Volt, Folded-Cascode OTA using the Current-Driven Bulk Technique
M6
Cx
VBiasP
+
vin M1 M2
-
M3 M5 M4
M11 M12
M9 M10
M7
vout
VDD
M17
VSS
VBiasN
CL
M8
M13
M14
M15
M16
Fig. 7.6-21
Transistors with forward-biased bulks are in a shaded box.
For large common mode input changes, Cx, is necessary to avoid slewing in the input
stage.
To get more voltage headroom at the output, the transistors of the cascode mirror have
their bulks current driven.
CMOS Analog Circuit Design © P.E. Allen - 2010

17. Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-33
A 1-Volt, Folded-Cascode OTA using the Current-Driven Bulk Technique -
Continued
Experimental results:
0.5μm CMOS, 40μA total bias current (Cx = 10pF)
Supply Voltage 1.0V 0.8V 0.7V
Common-mode input
range
0.0V-0.65V 0.0V-0.4V 0.0V-0.3V
High gain output range 0.35V-0.75V 0.25V-0.5V 0.2V-0.4V
Output saturation limits 0.1V-0.9V 0.15V-0.65V 0.1V-0.6V
DC gain 62dB-69dB 46dB-53dB 33dB-36dB
Gain-Bandwidth 2.0MHz 0.8MHz 1.3MHz
Slew-Rate (CL=20pF) 0.5V/μs 0.4V/μs 0.1V/μs
Phase margin (CL=20pF) 57° 54° 48°
The nominal value of bulk current is 10nA gives a 10% increase in differential pair
quiescent current assuming a BJT of 100.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 300 – Low Voltage Op Amps (3/28/10) Page 300-34
SUMMARY
• Integrated circuit power supplies are rapidly decreasing (today 2-3Volts)
• Classical analog circuit design techniques begin to deteriorate at 1.5-2 Volts
• Approaches for lower voltage circuits:
- Use natural NMOS transistors (VT 0.1V)
- Drive the bulk terminal
- Forward bias the bulk
- Use depeletion devices
• The dynamic range will be compressed if the noise is not also reduced
• Fortunately, the threshold reduction continues to allow the techniques of this section to
be used in today’s technology
CMOS Analog Circuit Design © P.E. Allen - 2010