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Igbt gate driver power supply flyback converter
1. IGBT Gate Driver Flyback Power Supply:
Design and Simulation using LTspice
Kunwar Aditya
January 06, 2019
2. Design
Features
๏ฑ Supports 3 IGBT Gate Drivers for Three-Phase Inverter
๏ฑ Operates with regulated (within 10%) 18 V supply
๏ฑ Output Power: 2 W per Gate Driver
๏ฑ Output Voltage: 24 V output per Gate Driver with ripple less than 1%
๏ฑ Split of 24 V rail into 16 V and -8V rails using a Zener diode and a series
resistor
๏ฑ Constant switching frequency of 100 kHz
๏ฑ External enable/disable circuit
3. Power supply Specifications
๏ฑ Vin: 15๏ฝ19VDC
๏ฑ Vout: 3 output of 24VDC at 260 mA total
๏ฑ Total Output Power, Pout: 6.2 W
๏ฑ Switching Frequency, fs: 100 kHz
๏ฑ Output Ripple Voltage โVo: 240mVp-p
Fig: Simplified Flyback schematic
LP LS
Iout
4. Design Steps: Determining operating mode
ITEM DCM CCM
Transformer
Inductance: down,
Size: down, Cost: down
Inductance: up, Size:
up, cost: up
Rectifier Diode FRD, Cost: down Ultra-FRD, Cost: up
MOSFET
Power: up, Size: up,
Cost: up
Power: down, Size:
down, Cost: down
Output Capacitor
Ripple current: up,
Size: up
Ripple current: down,
Size: up,
Efficiency
Switching loss: down*,
Efficiency: up
Switching loss: up,
Efficiency: down
Transient Response** Faster slower
Compensation** Much Simpler simple
Ts DTs D2Ts
(1-D-D2)Ts
IP
IS
Vds
CCM DCM
t
t
t
t
n*Vout
Vin
* ZCS at MOSFET turn on, ZCS at diode turn off.
**CCM mode has a significant RHP Zero which introduces phase lag therefore its close loop bandwidth is
limited and response is slower compared to DCM in which RHP zero is not significant.
Based on above comparison DCM is preferred choice for low power SMPS
Table: DCM Vs CCM
5. Design Steps: Calculation of circuit parameters
1. Set the reflected/flyback voltage (VOR):
๏ฑ When VOR is determined, turns ratio (n) and maximum duty cycle (Dmax) are fixed
๏ฑ Higher the duty ratio (D), smaller the primary current
๏ฑ Too high value of VOR increases voltage stress on MOSFET; too low value increases voltage stress on diode
๏ฑ Key Equations:
๐ ๐
๐ ๐
= ๐ =
๐ ๐๐
๐๐๐ข๐ก+๐ ๐
(I) ๐ท ๐๐๐ฅ =
๐ ๐๐
๐ ๐๐_๐๐๐+๐ ๐๐
(II)
๏ฑ If Dmax becomes > 0.5 at minimum input voltage (Vin_min) and maximum load, VOR needs to be adjusted to
keep it below 0.5
๏ฑ Dmax is usually decided by PMIC datasheet; 0.46 and 0.95 are typical values mentioned in PMIC datasheet
๏ฑ In deciding VOR margin must be given to consider forward recovery of the diode in clamp circuit as well as
load transients
๏ฑ For this power supply: VOR=12.5V, This gives Dmax=0.4545 and Assuming Vf=1V , n = 0.5
***Vf is forward voltage drop in rectifier diode
6. Design Steps: Calculation of circuit parameters
2. Calculate critical value of secondary inductance: LS, and secondary peak current: ISPK
๐ฟ ๐ =
๐๐๐ข๐ก+๐ ๐ ร 1โ๐ท ๐๐๐ฅ
2
2ร๐ผ ๐๐๐๐ฅร๐๐
(III)
๏ฑ To provide for a margin, such as an over-load protection point, the maximum load current Iomax should be 1.2
times the Iout.
๏ฑ Putting together all values, Ls =119 ยตH
๐ผ๐๐๐พ =
2ร๐ผ ๐๐๐๐ฅ
1โ๐ท ๐๐๐ฅ
= 1.2125 ๐ด (IV)
3. Calculate primary inductance LP and primary peak current IPPK
๐ฟ ๐ = ๐ฟ ๐ ร ๐2
= 29.750 ยต๐ป (V)
๐ผ ๐๐๐พ = ๐ผ๐๐๐พ ร ๐ = 2.425 ๐ด (VI)
๏ฑ Calculate RMS value of primary current IPRMS
๐ผ ๐๐ ๐๐ = ๐ผ ๐๐๐พ ร
๐ท ๐๐๐ฅ
3
= 0.9746 ๐ด (VII) **This is total secondary peak current
7. Design Steps: Calculation of circuit parameters
4. Calculate duty cycle, D and D2 for any input and output voltage
๐ท =
2๐ ๐ ๐ฟ ๐ ๐๐
๐ ๐๐
(VIII)
๐ท2 =
๐ ๐๐ร๐ท
๐ร ๐๐๐ข๐ก+๐ ๐
(IX)
๏ฑ Verify that D+D2 < 1 for DCM
5. Calculate auxiliary winding turn ratio
๐ ๐๐ข๐ฅ = ๐ ร
๐๐๐ข๐ก+๐ ๐
๐๐๐ข๐ฅ+๐ ๐
(X)
Here, Vaux is output of aux winding, naux is primary to aux turn ratio
๏ฑ For Vaux=24 V, naux= 0.5
๏ฑ Load on aux winding is usually the IC bias and MOSFET gate drive (~0.1 A)
8. Design Steps: Selection of MOSFET
๏ฑ Vds of MOSFET is calculated by the following eq:
๐๐๐ ๐๐๐ฅ = ๐๐๐๐๐๐ฅ + ๐๐๐ + ๐๐๐๐๐๐
= 19 + 12.5 + 1 โ 12.5
= 44 ๐ (I)
๏ฑ Vspike is voltage spike due to leakage inductance.
Assuming that a snubber will be added, a typical design
value is ยฝ of the flyback voltage (VOR). However, for this
power supply Vspike equal to VOR has been considered.
๏ฑ Current rating is usually selected to be twice of primary
peak current IPPK
Fig: Typical MOSFET Vds
9. Design Steps: Selection of Rectifier Diode
๏ฑ A fast output rectifier diode should be selected, e.g. a SBD (Schottky barrier diode) or a FRD (Fast recovery
diode)
๏ฑ Reverse Voltage Vdr to diode is given as:
๐๐๐ = ๐๐๐ข๐ก +
๐ ๐๐๐๐๐ฅ
๐
= 66.8 ๐ (I)
๏ฑ RMS current flowing diode is same as secondary current flowing in each winding ISRMS1
๐ผ๐๐ ๐๐1 =
2ร๐๐๐ข๐ก
3ร๐๐๐ข๐กร๐ท2
ร
๐ท2
3
(II)
๏ฑ Assuming maximum current flowing in each winding is 1.2 times the ISRMS1 we get 0.1435A
๏ฑ Select diode so that its VRRM (maximum reverse voltage) is at least 30% higher than Vdr and IF (Ave. forward
current) is at least 50% higher than the ISRMS1.
10. Design Steps: Selection of output capacitor
๏ฑ Output capacitors smooth ripples in the rectified voltage, and also serve to maintain stability during transient
increases in the load current.
๏ฑ Output capacitor is determined on the basis of peak to peak ripple voltage โVO , ESR and RMS current rating
๐ถ ๐๐๐๐ =
๐ท ๐๐๐ฅร๐ผ ๐๐ข๐ก
โ๐๐ร ๐๐
(I) โSelect capacitor value larger than thisโ
๐ธ๐๐ ๐๐๐ฅ =
โ๐๐
๐ผ ๐๐๐พ
(II) โSelect cap with ESR lower than this valueโ
๏ฑ Chose ESR value in datasheet at fs
๏ฑ Minimum RMS current of chosen CO is given as:
๐ผ ๐ถ๐๐ ๐๐ = ๐ผ๐๐ ๐๐
2
โ ๐ผ ๐๐ข๐ก
2
(III)
โThe combined RMS current rating of output cap(s) used should be higher than this valueโ
11. Nominal Parameters
Parameters Values
Duty cycle 0.3587
Peak Primary Current 2.3 A
Peak Secondary Current (Each secondary) 0.3559 A
Average Output Current (Each secondary) 0.0868 A
Voltage across MOSFET 31.5 V
Voltage across Diode 58 V
Voltage across LP during TON 17 V
Voltage across LP during TOFF -12.5 V
Voltage across LS during TON 34 V
Voltage across LS during TOFF -24 V
Table: DC Operating points for 24 V output at 6.2 W and Vin =17 V (obtained from
calculations)
12. Design Steps: Design of Clamp circuit
Fig : Current flow when switch is off
IP
Problem: Drain voltage with 3% leakage
Solution 1: Zener Clamp
Solution 2: RCD Clamp across MOSFET
Solution 3: RCD Clamp across Inductor
๐๐๐๐ = ๐๐๐ + ๐๐๐ + ๐ผ ๐๐๐พ
๐ฟ๐๐๐
๐ถ ๐๐
1. Zener Clamp:
๏ฑ Effectively clips the voltage spice until leakage energy is dissipated in
Zener diode
๏ฑ Only clamps when combine VOR and Vspike is greater than its
breakdown voltage; no power dissipation at light load
๏ฑ Dissipate more power at full load
๏ฑ Doesnโt damp ringing; may be difficult to pass EMI compliances
2. RCD clamp:
๏ฑ Cheaper than Solution 1
๏ฑ Dissipates power even under no load conditions as there is at least
VOR voltage across Rclamp at all time
๏ฑ Effective at even light load at the cost of efficiency
๏ฑ Not only clamps but also slows down MOSFET dV/dt, easier to meet
EMI compliances
๏ฑ Solution 2 needs to clamp voltage higher than VOR+Vin
๏ฑ Solution 3 needs to clamp voltage higher than VOR only
๏ฑ Dissipation of Rclamp in solution 2 for same amount of current will be
higher
3. Other solutions: active clamp, TVS, Zener across MOSFET
13. Design Steps: Design of RCD Clamp
๏ฑ Decide the clamp voltage Vclamp
๏ฑ The higher we select clamp voltage, the lower the overall dissipation
๏ฑ A typical design uses Vspike equal to ยฝ of VOR.
๏ฑ For this design Vspike equal to VOR has been selected
๏ฑ A value lower than Rclamp will cause less spike but more losses, a higher value will
cause more spike
Vclamp
Vspike
VOR
Fig : Drain voltage after adding clamp
Fig. Effectiveness of adding clamp
14. Design Step: Loop compensation
Fig : Simulation Results: Loop compensation using
pole/zero cancellation
Fig : Type II compensator
17. Simulation Results
Fig : Gate Voltage, ILP, ILS, Vout at full load (276.5 Ohm ) and one-third (800 Ohm) load at 24 Volt output, Vin is 17 V
1/3rd load
18. Simulation Results
Fig : Output voltage and current for step change in load
from half load to full load, Vin=17 V
Fig : Output voltage for different values of Vin
20. Important References used for this design
๏ฑ S. B. Yaakov, G. Ivensky, "Passive lossless snubbers for high frequency PWM converters", IEEE APEC'99, 1999-Mar
๏ฑ Ray Ridley, โFlyback Converter snubber designโ, Switching power magazine, 2005.
๏ฑ Ben-Yaakov, s. https://www.youtube.com/user/sambenyaakov/videos.
๏ฑ Claudio Adragna, โOffline flyback converters design methodology with the l6590 familyโ Application Note AN1262, [online] Available: https://www.st.com.
๏ฑ Sanjay Pithadia, N. Navaneeth Kumar, โAnalysis of Power Supply Topologies for IGBT Gate Drivers in Industrial Drivesโ Application Report SLAA672, [online]
Available: http://www.ti.com/lit/ug/tidu411/tidu411.pdf.
๏ฑ Allan A. Saliva, โDesign Guide for Off-line Fixed Frequency DCM Flyback Converterโ Design Note DN 2013-01, [online] Available:
https://www.mouser.com/pdfdocs/DN_201301.pdf