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Differential-In, Differential-Out Op Amp Lecture Guide
- 1. Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-1 LECTURE 280 – DIFFERENTIAL-IN, DIFFERENTIAL-OUT OP AMPS LECTURE ORGANIZATION Outline • Introduction • Examples of differential output op amps • Common mode output voltage stabilization • Summary CMOS Analog Circuit Design, 2nd Edition Reference Pages 384-393 CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-2 INTRODUCTION Why Differential Output Op Amps? • Cancellation of common mode signals including clock feedthrough • Increased signal swing v1 v2 v1-v2 A -A A -A t t 2A t -2A Fig. 7.3-1 • Cancellation of even-order harmonics Symbol: - - + + vin vout + + - - Fig. 7.3-1A CMOS Analog Circuit Design © P.E. Allen - 2010
- 2. Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-3 Common Mode Output Voltage Stabilization If the common mode gain not small, it may cause the common mode output voltage to be poorly defined. Illustration: vod VDD t t CM output voltage too small, Vcm 070506-01 0 VSS vod VDD t 0 VSS vod VDD 0 VSS CM output voltage properly defined, Vcm = 0 CM output voltage too large, Vcm = 0.5VDD = 0.5VSS Remember that: vOUT = Avd(vID) ± Acm(vCM) CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-4 EXAMPLES OF DIFFERENTIAL OUTPUT OP AMPS (OTA’S) Two-Stage, Miller, Differential-In, Differential-Out Op Amp Note that the upper ICMR is VDD - VSGP + VTN (OCMR) = VDD+ |VSS| - VSDP(sat) - VDSN(sat) The maximum peak-to-peak output voltage 2·OCMR VDD + - VBP M8 M6 M3 M4 Cc Rz Rz vo vi1 M1 M2 + - VBN M9 vo1 Conversion between differential outputs and single-ended outputs: + - vod CL + - + - + - vid + - VSS vo1 2CL + - +- + - vid + - vo2 2CL Fig. 7.3-4 M5 Cc vi2 M7 Fig. 7.3-3 CMOS Analog Circuit Design © P.E. Allen - 2010
- 3. Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-5 Two-Stage, Miller, Differential-In, Differential-Out Op Amp with Push-Pull Output M13 M14 vo1 Rz Rz vo2 vi1 VDD + - VBP M3 M4 M1 M2 M5 M6 M7 M10 M12 VSS + - VBN Cc M9 Cc vi2 M8 Fig. 7.3-6 Comments: • Able to actively source and sink output current • Output quiescent current poorly defined CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-6 Folded-Cascode, Differential Output Op Amp VDD I4 I5 M4 M5 I7 M6 M7 C − vOUT + L M8 M9 VNB1 M10 M11 CL 060717-01 VPB1 I6 VPB2 VNB2 + − vIN I1 I2 VNB1 M1 M2 M3 I3 • No longer has the low-frequency asymmetry in signal path gains. • Class A CMOS Analog Circuit Design © P.E. Allen - 2010
- 4. Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-7 Enhanced-Gain, Folded-Cascode, Differential Output Op Amp What about the A amplifier? Below is the upper A amplifier: M7 M8 M9 M10 + vin - VPB2 VPB2 - M1 M2 M3 vout + vout M12 060718-02 VDD VPB1 vin VNB1 VBias M4 M5 M6 M11 Note that VBias controls the dc voltage at the input of the A amplifier through the negative feedback loop. VPB1 + − M1 M2 060718-01 M3 vIN VNB1 • Balanced inputs • Class A VDD VPB1 M10 M11 +A − + − M8 M9 − + vOUT M4 M7 M5 M6 − + − A + CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-8 Push-Pull Cascode Op Amp with Differential-Outputs VDD M7 M5 M3 M4 M6 M8 M21 M9 M10 vi1 M1 M2 vi2 vo2 M15 M16 M17 vo1 M13 M12 VSS VBias R2 M22 M23 R1 M20 M19 M11 M14 M18 Fig. 7.3-8 • Output quiescent currents are well defined • Self-biased circuits can be replaced with VNB2 and VPB2 CMOS Analog Circuit Design © P.E. Allen - 2010
- 5. Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-9 Folded-Cascode, Push-Pull, Differential Output Op Amp I7 I9 0.5gm2vin 0.5gm4vin I8 M8 M9 0.5g 0.5gm4vin m2vin vOUT CL CL − + 0.5gm3vin 0.5gm1vin M10 M11 M12 M13 060717-02 VPB1 M6 M7 I6 I4 VPB2 VNB2 + − I14 I15 I17 M16 M17 vIN I2 VDD M2 M3 I1 M1 VNB1 I3 M5 I5 VNB2 M4 M18 M19 M20 M21 VPB1 M14 M15 I16 VPB2 0.5gm1vin 0.5gm3vin I6 = I7 = I14 = I15 0.5I5 I5 = I1 + I2 + I3 + I4 Av = gmRout(diff) CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-10 Enhanced-Gain, Folded-Cascode with Push-Pull Outputs VPB1 M10 M11 VPB2 M12 M13 060718-06 VPB1 M6 M7 +A − + − M8 M9 vOUT CL CL − + M18 M20 M19 VNB2 M21 + − vIN VDD M2 M3 M1 VNB1 M5 M4 VNB2 M14 M15 M16 M17 − A + − + • Gain approaches gm 3rds 3 CMOS Analog Circuit Design © P.E. Allen - 2010
- 6. Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-11 Cross-Coupled Differential Amplifier Stage The cross-coupled input stage allows the push-pull output quiescent current to be well defined. i1 M1 M2 + vGS1 - + vGS2 - vi1 vi2 + vSG4 M3 M4 VGS2 VSG4 VGS1 VSG3 i2 i2 i1 Fig. 7.3-9 - + vSG3 - Operation: Voltage loop vi1 - vi2 = -VGS1+ vGS1 + vSG4 - VSG4 = VSG3 - vSG3 - vGS2 + VGS2 Using the notation for ac, dc, and total variables gives, vi2 - vi1 = vid = (vsg1 + vgs4) = -(vsg3 + vgs2) If gm1 = gm2 = gm3 = gm4, then half of the differential input is applied across each transistor with the correct polarity. i1 = gm1vid 2 = gm4vid 2 and i2 = - gm2vid 2 = - gm3vid 2 CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-12 Class AB, Differential Output Op Amp using a Cross-Coupled Differential Input Stage VDD M9 M7 M8 M10 vi1 vi2 M1M2 M21 M22 M19 M20 M3 M4 M13 M14 vo1 M15 vo2 M16 M17 M18 M26 M23 M11 M12 M5 M6 VSS + R2 M28 VBias - M25 R1 M24 M27 Fig. 7.3-10 Quiescent output currents are defined by the current in the input cross-coupled differential amplifier. CMOS Analog Circuit Design © P.E. Allen - 2010
- 7. Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-13 COMMON MODE OUTPUT VOLTAGE STABILIZATION Common Mode Feedback Circuits Because the common mode gain is undefined, any common mode signal at the input can cause the output common mode voltage to be improperly defined. The common mode output voltage is stabilized by sensing the common mode output voltage and using negative feedback to adjust the common mode voltage to the desired value. Model for the Output of Differential Output Op Amps: VDD io1(source) Ro1 vo1 io1(sink) Ro3 io2(source) vo2 io2(sink) Ro2 Ro4 VDD io1(source) Ro1 vo1 Io1(sink) Ro3 io2(source) vo2 Io2(sink) Ro2 Ro4 Class A Output Push-Pull Output 060718-08 Roi represents the self-resistance of the output sink/sources. 1.) If the common mode output voltage increases the sourcing current is too large. 2.) If the common mode output voltage decreases the sinking current is too large. CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-14 Conceptual View of Common-Mode Feedback 060718-09 VDD Common Mode Sensing Circuit VCMREF + − vo2 vo1 Output Stage Model Function of the common-mode feedback circuit: 1.) If the common-mode output voltage increases, decrease the upper currents sources or increase the lower current sink until the common-mode voltage is equal to VCMREF. 2.) If the common-mode output voltage decreases, increase the upper currents sources or decrease the lower current sink until the common-mode voltage is equal to VCMREF. CMOS Analog Circuit Design © P.E. Allen - 2010
- 8. Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-15 Two-Stage, Miller, Differential-In, Differential-Out Op Amp with Common-Mode Feedback VDD + M10 M11 VBP - M7 M6 M3 M4 Cc Rz Rz vo2 vi1 M1 M2 M5 VSS + - VBN Cc M9 vi2 vo1 M8 Fig. 7.3-12 Comments: • Simple • Unreferenced – value of common mode output voltage determined by the circuit characteristics CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-16 Common Mode Feedback Circuits Implementation of common mode feedback circuit: M3 M4 I3 I4 Ro1 Ro2 M1 M2 vo2 vi2 060718-10 vi1 M5 VDD IBias Common-mode feed-back circuit VCM vo1 IC3 IC4 MC2A MC4 MC2B MC1 MC3 MC5 MB This scheme can be applied to any differential output amplifier. CM Loop Gain = -gmC1Ro1 which can be large if the output of the differential output amplifier is cascaded or a gain-enhanced cascode. The common-mode loop gain may need to be compensated for proper dynamic performance. CMOS Analog Circuit Design © P.E. Allen - 2010
- 9. Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-17 Common Mode Feedback Circuits – Continued The previous circuit suffers when the input common mode voltage is low because the transistors MC2A and MC2B have a poor negative input common mode voltage. The following circuit alleviates this disadvantage: M3 M4 I3 I4 vo1 vo2 RCM1 RCM2 M1 M2 vi2 060718-11 vi1 M5 VDD IBias Common-mode feed-back circuit VCM MC3 IC4 IC3 MC1 MC2 MC4 MC5 MB CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-18 An Improved Common-Mode Feedback Circuit The resistance loading of the previous circuit can be avoided in the following CM feedback implementation: VDD CM Correction Circuitry M5 M6 M1 M2 M3 M4 vo1 vo2 060718-12 RCM RCM VCMREF This circuit is capable of sustaining a large differential voltage without loading the output of the differential output op amp. CMOS Analog Circuit Design © P.E. Allen - 2010
- 10. Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-19 Frequency Response of the CM Feedback Circuit Consider the following CM feedback circuit implementation: − + M12 M13 M14 Cc M3 VCMREF 070506-02 VPB1 M4 M5 VPB2 VDD M6 M7 vOUT VNB2 M8 M10 M9 M11 + − vIN VNB1 M1 M2 M15 M16 Cc The CM feedback path has two poles – one at the gates of M10 and M11 and the dominant output pole of the differential output op amp. Can compensate with Miller capacitors as shown. CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-20 Improved CM Feedback Frequency Response The circuit on the previous page can be modified to eliminate the pole at the gates of M10 and M11 as follows: VCMREF 060718-14 VPB1 M4 M5 VPB2 VDD M6 M7 VNB2 M8 vo1 M9 VNB1 vo2 M10 M11 + − vin VNB1 M1 M2 M3 M12 M13 M14 VNB2 M19 M18 M16 M15 M17 • The need for compensation of the common mode loop no longer exists since there is only one dominant pole • The dominant pole of the differential amplifier becomes the dominant pole of the common mode feedback CMOS Analog Circuit Design © P.E. Allen - 2010
- 11. Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-21 A Common Mode Feedback Correction Scheme for Discrete Time Applications Correction Scheme: φ1 φ2 vo1 φ1 + Ccm - +- + - vid CMbias vo2 φ1 Ccm Vocm φ1 φ2 φ1 Fig. 7.3-14 Operation: 1.) During the 1 phase, both Ccm are charged to the desired value of Vocm and CMbias = Vocm. 2.) During the 2 phase, the Ccm capacitors are connected between the differential outputs and the CMbias node. The average value applied to the CMbias node will be Vocm. CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-22 Example of a Common-Mode Output Voltage Stabilization Scheme for Discrete- Time Applications Common mode adjustment phase: Switches S1, S2 and S3 are closed. C1 and C2 are charged to the value necessary for I12 and I13 to keep the common mode output voltage at VCM. Amplification phase: Switches S4 and S5 are closed. If the common mode output voltage is not at VCM, the currents I12 and I13 will change to force the value of the common mode output voltage back to VCM. M15 Discrete time common mode correction circuit S4 C1 C2 S5 S1 S2 S3 M12 M13 M14 070506-03 VPB1 M4 M5 VPB2 VDD M6 M7 − + vOUT VNB2 M8 M9 VNB1 I12 I13 M10 M11 + − vIN VNB1 M1 M2 M3 VCM CMOS Analog Circuit Design © P.E. Allen - 2010
- 12. Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-23 Correction of Channel Charge and Clock Feedthrough In the discrete-time common mode correction schemes, the switches can introduce error due to channel charge and clock feedthrough. Through simulation, these errors can be predicted and corrected by applying a correction signal superimposed upon the error signal to achieve the desired (target) common mode voltage. General principle: Unwanted Charge Injection Error CMFB Amplifier CMFB Sense Differential Outputs VBias ΔV Vcm (Target voltage) Correction Signal Error Signal CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 280 – Differential-In, Differential-Out Op Amps (3/28/10) Page 280-24 SUMMARY • Advantages of differential output op amps: - 6 dB increase in signal amplitude - Cancellation of even harmonics - Cancellation of common mode signals including clock feedthrough • Disadvantages of differential output op amps: - Need for common mode output voltage stabilization - Compensation of common mode feedback loop - Difficult to interface with single-ended circuits • Most differential output op amps are truly balanced • For push-pull outputs, the quiescent current should be well defined • Common mode feedback schemes include, - Continuous time - Discrete time CMOS Analog Circuit Design © P.E. Allen - 2010