1. Lecture 260 – Buffered Op Amps (3/28/10) Page 260-1
LECTURE 260 – BUFFERED OP AMPS
LECTURE ORGANIZATION
Outline
• Introduction
• Open Loop Buffered Op Amps
• Closed Loop Buffered Op Amps
• Use of the BJT in Buffered Op Amps
• Summary
CMOS Analog Circuit Design, 2nd Edition Reference
Pages 352-368
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-2
INTRODUCTION
Buffered Op Amps
What is a buffered op amp?
Buffered op amps are op amps with the ability to drive a low output resistance and/or
a large output capacitance. This requires:
- An output resistance typically in the range of 10 Ro 1000
- Ability to sink and source sufficient current (CL·SR)
Rout
Large
Rout
Small
+
−
Op Amp Buffer
vIN vOUT
vOUT’
070430-01
Types of buffered op amps:
- Open loop using output amplifiers
- Closed loop using negative shunt feedback to reduce the output resistance of the op
amp
CMOS Analog Circuit Design © P.E. Allen - 2010

2. Lecture 260 – Buffered Op Amps (3/28/10) Page 260-3
OPEN LOOP BUFFERED OP AMPS
The Class A Source Follower as a Buffer
• Simple
gm
• Small signal gain
gm+gmbs+GL 1
• Low efficiency
1
• Rout =
gm+gmbs 500 to 1000
VDD
M1
vIN
VNBias1
M2
vOUT
• Level shift from input to output
060118-10
• Maximum upper output voltage is limited
• Broadbanded as the pole and zero due to the source follower are close so compensation
is typically not a problem
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-4
The Push-Pull Follower as a Buffer
• Voltage loss from 2 cascaded followers
Av
gm3+gmbs3
gm3
gm1
gm1+gmbs1+GL 1
• Higher efficiency
0.5
• Rout
gm+gmbs 250 to 500
• Current in M1 and M2 determined by:
VGS4 + VSG3 = VGS1 + VSG2
2I6
Kn'(W4/L4) +
2I5
Kp'(W3/L3)
=
2I1
Kn'(W1/L1) +
2I2
Kp'(W2/L2)
VDD
M5
I5
VDD
VPBias1
+
VSG3
M3
−
+
−
VGS1
I1
vIN vOUT
Use the W/L ratios to define I1 and I2 from I5 and I6
+ VSG2
−
VGS4
VNBias1
• Maximum positive and negative output voltages are limited
VDD
I2
060706-02
VDD
M1
+
M2
M4
VDD
I6
M6
−
CMOS Analog Circuit Design © P.E. Allen - 2010

3. Lecture 260 – Buffered Op Amps (3/28/10) Page 260-5
Two-Stage Op Amp with Follower
-
vin
+
M3 M4
M1 M2
M5
M6
VDD
M7
VNBias
Cc
vout
CL
I5
I7
M8
I9
060706-03
M9
Power dissipation now becomes (I5 + I7 + I9)VDD
Gain becomes,
Av =
gm1
gds2+gds4
gm6
gds6+gds7
gm8
gm8+gmbs8+gds8+gds9
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-6
Source-Follower, Push-Pull Output Op Amp
VSS
vout
VDD
CL
VDD
Cc
IBias
+
vin
-
R1
M6
M5
M8
M7
M1 M2
M3
M11
M12
R1
M13
M14
VSS
R1
M17
I17
VDD
VSS
M22
+
VGS22
-
VSG21 +
-
M21
M9
M10
M4
VSG18 +
-
M18
M15
M19
+
VGS19
M16
I20
M20
Fig. 7.1-1
Buffer
-
Rout
1
gm21+gm22 1000, Av(0)=65dB (IBias=50μA), and GB = 60MHz for CL = 1pF
Note the bias currents through M18 and M19 vary with the signal.
CMOS Analog Circuit Design © P.E. Allen - 2010

4. Lecture 260 – Buffered Op Amps (3/28/10) Page 260-7
Compensation of Op Amps with Output Amplifiers
Compensation of a three-stage amplifier:
This op amp introduces a third pole, p’3 (what
about zeros?)
With no compensation,
Vout(s)
Vin(s) =
-Avo
s
p’1-1
s
p’2-1
s
p’3-1
Illustration of compensation choices:
p2
p3' p2' p1' p1
p3
jω
σ
Poles
p1' and p2'
Pole p3'
vin vout +-
Unbuffered
op amp
+
-
Compensated poles
Uncompensated poles
p2
v2
p3' p2' p1' p1
p3=
x1
Output
stage
jω
σ
Miller compensation applied around
both the second and the third stage.
CL RL
Miller compensation applied around
the second stage only. Fig. 7.1-5
Fig. 7.1-4
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-8
Crossover-Inverter, Buffer Stage Op Amp
Principle: If the buffer has high output resistance and voltage gain (common source), this
is okay if when loaded by a small RL the gain of this stage is approximately unity.
vout
RL
060706-04
-
+
vin
VDD
M3 M4
M7 M6
C2
IBias
C1
M1 M2
M5
Cross over stage Output Stage
VSS
-
+
Input
stage
vin'
• This buffer trades gain for the ability to drive a low load resistance
• The load resistance should be fixed in order to avoid changes in the buffer gain
• The push-pull common source output will give good output voltage swing capability
CMOS Analog Circuit Design © P.E. Allen - 2010

5. Lecture 260 – Buffered Op Amps (3/28/10) Page 260-9
Crossover-Inverter, Buffer Stage Op Amp - Continued
How does the output buffer work?
The two inverters, M1-M3 and M2-M4 are designed to work over different regions of the
buffer input voltage, vin’.
Consider the idealized voltage transfer characteristic of the crossover inverters:
VDD vout
M6 Active
M6 Satur-ated
M2-M4
Inverter
0 vin'
VA VDD
060706-05
M1-M3
Inverter
M5 Saturated
M5 Active
VB
VDD
M7 M3 M4
C1 C2
M1 M2
vout
VSS
IBias
vin'
M6
M5 RL
VSS
Crossover voltage VC = VB-VA 0
VC is designed to be small and positive for worst case variations in processing.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-10
Large Output Current Buffer
In the case where the load consists of a large capacitor, the ability to sink and source a
large current is much more important than reducing the output resistance. Consequently,
the common-source, push-pull is ideal if the quiescent current can be controlled.
A possible implementation:
If W4/L4 = W9/L9 and
W3/L3 = W8/L8, then the
quiescent currents in M1
and M2 can be determined
by the following
relationship:
I1 = I2 = Ib
W1/L1
W7/L7
vin
= Ib
VDD
vout
VSS
W2/L2
W10/L10
VDD
I=2Ib
M8 M9
I=2Ib
VSS
Ib
Ib
M1
vout
M2
M5
M3 M4
M6
M7
M10
vin
070430-07
When vin is increased, M6 turns off M2 and turns on M1 to source current. Similarly,
when vin is decreased, M5 turns off M1 and turns on M2 to sink current.
CMOS Analog Circuit Design © P.E. Allen - 2010

6. Lecture 260 – Buffered Op Amps (3/28/10) Page 260-11
CLOSED LOOP BUFFERED OP AMPS
Principle
Use negative shunt feedback to reduce the output resistance of the buffer.
Av
+
−
vIN
Ro ROUT
vOUT
070430-02
RL
• Output resistance
ROUT =
Ro
1+Av
• Watch out for the case when RL causes Av to decrease.
• The bandwidth will be limited by the feedback (i.e. at high frequencies, the gain of Av
decreases causing the output resistance to increase.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-12
Two Stage Op Amp with a Gain Boosted, Source Follower Buffer
-
vin
+
M3 M4
M1 M2
M5
M6
VDD
M7
VNBias
Cc
I5
I7
M9 M10
Rout
vout
I11
070430-03
1:K
M8
M11
Rout
1
gm8K
Power dissipation now becomes (I5 + I7 + I11)VDD
Gain becomes,
Av =
gm1
gds2+gds4
gm6
gds6+gds7
gm8K
gm8K+gmbs8K+GL
CMOS Analog Circuit Design © P.E. Allen - 2010

7. Lecture 260 – Buffered Op Amps (3/28/10) Page 260-13
Gain Boosted, Source-Follower, Push-Pull Output Op Amp
VDD
Cc
M24
+
vin
-
M5
M8
M1 M2
+
VT+2VON
-
M23 I20
M3
M11
M12
R1
M13
M14
VSS
M6
M7
M17
I17
VDD
VSS
M23 M24
M22
+
VGS22
-
VSG21 +
-
M21
IBias
M9
M10
M4
VSG18 +
-
M18
M15
M19
+
VGS19
M16
1:K
M25 M26
M20
Gain Enhanced Buffer
-
Rout
vout
1:K
070430-04
Rout
1
K(gm21+gm22)
1000
K 100
Av(0)=65dB (IBias=50μA)
Note the bias currents through M18 and M19 vary with the signal.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-14
Common Source, Push Pull Buffer with Shunt Feedback
To get low output resistance using MOSFETs, negative feedback must be used.
Ideal implementation:
VDD
M2
iout
Error
Amplifier
- +
- +
Gain
Amplifier
viin vout
CL RL
M1
Fig. 7.1-5A
Error
Amplifier
VSS
+ -
Comments:
• The output resistance will be equal to rds1||rds2 divided by the loop gain
• If the error amplifiers are not perfectly matched, the bias current in M1 and M2 is not
defined
CMOS Analog Circuit Design © P.E. Allen - 2010

8. Lecture 260 – Buffered Op Amps (3/28/10) Page 260-15
Low Output Resistance Op Amp - Continued
Offset correction circuitry:
+
vin
-
VDD
M6
M16 M9
A1
vout
M8A
VOS
VSS
Cc
Unbuffered
op amp
+
-
VBias
+-
- +
Error Loop
- +
M8
M17
M13
M6A
M10
M12 M11
A2
Fig. 7.1-6
The feedback circuitry of the two error amplifiers tries to insure that the voltages in
the loop sum to zero. Without the M9-M12 feedback circuit, there is no way to adjust the
output for any error in the loop. The circuit works as follows:
When VOS is positive, M6 tries to turn off and so does M6A. IM9 reduces thus reducing
IM12. A reduction in IM12 reduces IM8A thus decreasing VGS8A. VGS8A ideally decreases
by an amount equal to VOS. A similar result holds for negative offsets and offsets in EA2.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-16
Low Output Resistance Op Amp - Continued
Error amplifiers:
vin
M3 M4
M1 M2
M5
VDD
M6
vout
M6A
VSS
+
-
VBias
Cc1
A1 amplifier
MR1
+
-
VBias
M5A
M2A M1A
M4A M3A
A2 amplifier
070430-05
vin
MR2
Cc2
Basically a two-stage op amp with the output push-pull transistors as the second-stage of
the op amp.
CMOS Analog Circuit Design © P.E. Allen - 2010

9. Lecture 260 – Buffered Op Amps (3/28/10) Page 260-17
Low Output Resistance Op Amp - Complete Schematic
+
-
v M3H M4H MP4
M5A in
M3 M4
M2
M1
M17 MN3 MN4
M5
VDD
M16
Cc
VSS
+
-
+-
VBiasN
Cc1
MP3
MP5
MR1
M8
M6
M6A
MR2
M8A
Cc2
M9
M10
M13 M12 M11
Short circuit protection(max. output ±60mA):
MP3-MN3-MN4-MP4-MP5
MN3A-MP3A-MP4A-MN4A-MN5A
Rout
rds6||rds6A
LoopGain
50k
5000 = 10
M2A M1A
M4A M3A
vout
+
-
VBiasP
MP4A
MN5A
MN4A
MP3A
MN3A
M4HA
M3HA
Fig. 7.1-8
RC
CC
gm1 gm6
R1 C1
RL CL
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-18
Simpler Implementation of Negative Feedback to Achieve Low Output Resistance
Output Resistance:
Rout =
Ro
1+LG
where
Ro =
1
gds6+gds7
and
|LG| =
gm2
2gm4
(gm6+gm7)Ro
Therefore, the output resistance is:
+
vin
200μA 10/1 1/1 10/1
1/1
M10
Rout =
VDD
M3 M4
M1 M2
10/1 10/1
M5
1/1
1/1
10/1 10/1
VSS
1
M8
M9
(gds6+gds7)
M6
M7
CL
Fig. 7.1-9
gm2
2gm4 (gm6+gm7)Ro

11. 1+
-
vout
CMOS Analog Circuit Design © P.E. Allen - 2010

12. Lecture 260 – Buffered Op Amps (3/28/10) Page 260-19
Example 260-1 - Low Output Resistance Using Shunt Negative Feedback Buffer
Find the output resistance of above op amp using the model parameters of KN’ =
120μA/V2, KP’ = 25μA/V2, N = 0.06V-1 and P = 0.08V-1.
Solution
The current flowing in the output transistors, M6 and M7, is 1mA which gives Ro of
Ro =
1
(N+P)1mA =
1000
0.14 = 7.143k
To calculate the loop gain, we find that
gm2 = 2KN’·10·100μA = 490μS
gm4 = 2KP’·1·100μA = 70.7μS
and
gm6 = 2KP’·10·1000μA = 707μS
Therefore, the loop gain is
|LG| =
490
2·70.7 (0.707+0.071)7.143 = 19.26
Solving for the output resistance, Rout, gives
Rout =
7.143k
1+19.26 = 353 (Assumes that RL is large)
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-20
USE OF THE BJT IN BUFFERED OP AMPS
Substrate BJTs
Illustration of an NPN substrate BJT available in a p-well CMOS technology:
Emitter Base Collector
n+ (Emitter) p+
p- well (Base)
n- substrate (Collector)
(VDD)
n
+
Collector (VDD)
Emitter
Base
Fig. 7.1-10
Comments:
• gm of the BJT is larger than the FET so that the output resistance w/o feedback is lower
• Collector current will be flowing in the substrate
• Current is required to drive the BJT
• Only an NPN or a PNP bipolar transistor is available
CMOS Analog Circuit Design © P.E. Allen - 2010

13. Lecture 260 – Buffered Op Amps (3/28/10) Page 260-21
A Lateral Bipolar Transistor
n-well CMOS technology:
• It is desirable to have the lateral
collector current much larger than the
vertical collector current.
• Triple well technology allows the
current of the vertical collector to avoid
flowing in the substrate.
• Lateral BJT generally has good
matching.
VC B E LC
060221-01
p+
LC
p+ p+
STI STI
n-well
n+
Substrate
STI Lateral Collector
Emitter
Base
Vertical
Collector
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-22
A Field-Aided Lateral BJT
Use minimum channel length to
enhance beta:
ßF 50 to 100 depending on the
process
VC B
060221-02
E LC
p+
LC
p+ p+ p+
Keeps carriers from
flowing at the surface
and reduces 1/f noise
STI STI
n-well
n+
Substrate
STI Lateral Collector Emitter
Base
Vertical
Collector
CMOS Analog Circuit Design © P.E. Allen - 2010

14. Lecture 260 – Buffered Op Amps (3/28/10) Page 260-23
Two-Stage Op Amp with a Class-A BJT Output Buffer Stage
Purpose of the M8-M9 source
follower:
1.) Reduce the output resistance
(includes whatever is seen from
the base to ground divided by
1+F)
2.) Reduces the output load at the
drains of M6 and M7
Small-signal output resistance :
r10+(1/gm9)
Rout
1+ßF
=
1
gm10
+
M12
M13
1
+
vin
-
IBias
gm9(1+ßF)
M5
M1 M2
VDD
M3 M4
M7
Q10
M8
M9
Cc CL
M6
vout
VSS
M11
RL
Fig. 7.1-11
Output Buffer
= 51.6+6.7 = 58.3 where I10=500μA, I8=100μA, W9/L9=100 and ßF is 100
vOUT(max) = VDD - VSD8(sat) - vBE10 = VDD -
2KP’
I8(W8/L8) - Vt ln
Ic10
Is10
Voltage gain:
vout
vin
gm1
gds2+gds4
gm6
gds6+gds7
gm9+gmbs9+gds8+g10
gm9
gm10RL
1+gm10RL
Compensation will be more complex because of the additional stages.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-24
Example 260-2 - Designing the Class-A, Buffered Op Amp
Use an n-well, 0.25μm CMOS technology to design an op amp using a class-A, BJT
output stage to give the following specifications. Assume the channel length is to be
0.5μm. The FETs have the model parameters of KN’ = 120μA/V2, KP’ = 25μA/V2, VTN =
|VTP| = 0.5V, N = 0.06V-1 and P = 0.08V-1 along with the BJT parameters of Is =
10-14A and ßF = 50.
VDD = 2.5V VSS = 0V GB = 5MHz Avd(0) 2500V/V Slew rate 10V/μs
RL = 500 Rout 50 CL = 100pF ICMR = +1V to 2V
Solution
A quick comparison shows that the
specifications of this problem are similar
to the folded cascode op amp that was
designed in Ex. 240-3. Borrowing that
design for this example results in the
following op amp.
Therefore, the goal of this example
will be the design of M12 through Q15 to
satisfy the slew rate and output resistance
requirements.
M14
I15
Rout
vO
C
Q15
070430
VDD
VPB1
I4 I5
M4 M5
I6
VPB2
I7
M6 M7
VNB2
M8 M9
M10
M11
+
−
vIN
I1 I2
VNB1
M1 M2
M3
I3
VNB1
VPB1
I12
M12
M13
CMOS Analog Circuit Design © P.E. Allen - 2010

15. Lecture 260 – Buffered Op Amps (3/28/10) Page 260-25
Example 260-2 – Continued
BJT follower (Q15):
SR = 10V/μs and 100pF capacitor give I15 = 1mA.
Assuming the gate of M14 is connected to the gate of M5, the W/L ratio of M14
becomes
W14/L14 = (1000μA/125μA)160 = 1280 W14 = 640μm
I15 = 1mA 1/gm15 = 0.0258V/1mA = 25.8
MOS follower:
To source 1mA, the BJT requires 20μA (ß =50) from the MOS follower (M12-M13).
Therefore, select a bias current of 100μA for M13. If the gates of M3 and M13 are
connected together, then
W13/L13 = (100μA/100μA)15 = 15 W13 = 7.5μm
To get Rout = 50, if 1/gm15 is 25.8, then design gm12 as
1
gm15
=
1
gm12(1+ßF) = 24.2 gm12 =
1
(24.2)(1+ßF) =
1
24.2·51 = 810μS
gm12 and I12 W/L = 27.3 30 W12 = 15μm
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 260 – Buffered Op Amps (3/28/10) Page 260-26
Example 260-2 - Continued
To calculate the voltage gain of the MOS follower we need to find gmbs9 (N = 0.4 V).
gmbs12 =
gm12N
2 2F+VBS12
=
810·0.4
2 0.5+0.55 = 158μS
where we have assumed that the value of VSB12 is approximately 1.25V – 0.7V = 0.55V.
AMOS =
810μS
810μS+158μS+6μS+8μS = 0.825
The voltage gain of the BJT follower is
ABJT =
500
25.8+500 = 0.951 V/V
Thus, the gain of the op amp is
Avd(0) = (3,678)(0.825)(0.951) = 2,885 V/V
The power dissipation of this amplifier is,
Pdiss. = 2.5V(125μA+125μA+100μA+1000μA) = 3.375mW
The signal swing across the 500 load resistor will be restricted to ±0.5V due to the
1000μA output current limit.
CMOS Analog Circuit Design © P.E. Allen - 2010

16. Lecture 260 – Buffered Op Amps (3/28/10) Page 260-27
SUMMARY
• A buffered op amp requires an output resistance between 10 Ro 1000
• Output resistance using MOSFETs only can be reduced by,
- Source follower output (1/gm)
- Negative shunt feedback (frequency is a problem in this approach)
• Use of substrate (or lateral) BJT’s can reduce the output resistance because gm is
larger than the gm of a MOSFET
• Adding a buffer stage to lower the output resistance will most likely complicate the
compensation of the op amp
CMOS Analog Circuit Design © P.E. Allen - 2010