1. Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-1
LECTURE 290 – LOW POWER AND LOW NOISE OP AMPS
LECTURE ORGANIZATION
Outline
• Review of subthreshold operation
• Low power op amps
• Review of MOSFET noise modeling and analysis
• Low noise op amps
• Summary
CMOS Analog Circuit Design, 2nd Edition Reference
Pages 393-414
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-2
REVIEW OF SUBTHRESHOLD OPERATION
Subthreshold Operation
Most micropower op amps use transistors in the subthreshold region.
Subthreshold characteristics:
The model that has
been developed for
the large signal sub-threshold
operation
is:
iD = It
WL
exp
vGS-VT
nVt
Square Law Strong Inversion
iD
1μA
100nA
Transition
100nA
Weak Inversion
Exponential
vGS
iD
vGS =VT
vGS ≤VT
vDS
0 0
0
VT
0 1V 2VFig. 7.4-0A
vDS
VA where vDS 0 and VDS(sat) = VON = VGS -VT = 2nVt
1+
Small-signal model:
gm =
diD
dvGS |Q
= It
WL
It
nVt exp
vGS-VT
nVt
vDS
VA =
1+
ID
nVt =
qID
nkT =
ID
Vt
Cox
Cox+Cjs
gds =
diD
dvDS |Q
ID
VA
CMOS Analog Circuit Design © P.E. Allen - 2010

2. Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-3
Boundary Between Subthreshold and Strong Inversion
It is useful to develop a means of estimating when a MOSFET is making the transition
between subthreshold and strong inversion to know when to use the proper model.
The relationship developed is based on the following concept:
We will solve for the value of vGS
(actually vGS -VT) and find the drain
current where these two values are
equal [vGS(tran.) -VT)].
The large signal expressions for each
region are:
Subthreshold-iD
It
WL
exp
iD
ItW vGS-VT
L
exp( )
iD = nVt
iD(tran.)
vGS(tran.) 070507-01
vGS-VT
nVt vGS-VT = nVt ln
iD = (vGS-VT K‘W )2
iD
2L
VT
It(W/L) nVt
vGS
1-
It(W/L)
iD
if 0.5 iD/(ItW/L).
Strong inversion-iD
=
K'W
2L
vGS-VT 2 vGS-VT =
2iD
K'(W/L)
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-4
Boundary Between Subthreshold and Strong Inversion - Continued
Equating the two large signal expressions gives,
nVt
It(W/L)
iD =
1-
2iD
K'(W/L) n2Vt
2
1-
It(W/L)
iD
2
=
2iD
K'(W/L)
Expanding gives,
2
n2Vt
2 =
iD +1 n2Vt
It2(W/L)2
iD
2It(W/L)
2 -
2iD
K'(W/L) if (ItW/L)/iD 0.5
Therefore we get,
iD(tran.) =
K'W
2L n2Vt
2
For example, if K’ = 120μA/V2, W/L = 100, and n = 2, then at room temperature the
value of drain current at the transition between subthreshold and strong inversion is
iD(tran.) =
120μA/V2100
2 4·(0.026)2 = 16.22μA
One will find for UDSM technology, that weak inversion or subthreshold operation can
occur at large currents for large values of W/L.
CMOS Analog Circuit Design © P.E. Allen - 2010

3. Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-5
LOW POWER OP AMPS
Two-Stage, Miller Op Amp Operating in Weak Inversion
-
vin
+
M3 M4
M1 M2
M5
M6
M7
vout
VDD
VSS
+
-
VBias
Cc
CL
Fig.7.4-1
Low frequency response:
Avo = gm2gm6
ro2ro4
ro2+ro4
ro6ro7
ro6+ro7 =
1
n2n6(kT/q)2(2+4)(6+7) (No longer
1
ID
)
GB and SR:
GB =
ID1
(n1kT/q)C and SR =
ID5
C = 2
ID1
C = 2GB
kT
q = 2GBn1Vt
n1
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-6
Example 290-1 Gain and GB Calculations for Subthreshold Op Amp.
Calculate the gain, GB, and SR of the op amp shown above. The currents are ID5 =
200 nA and ID7 = 500 nA. The device lengths are 1 μm. Values for n are 1.5 and 2.5 for
p-channel and n-channel transistors respectively. The compensation capacitor is 5 pF.
The channel length modulation parameters are N = 0.06V-1 and P = 0.08V-1. Assume
that the temperature is 27 °C. If VDD = 1.5V and VSS = -1.5V, what is the power
dissipation of this op amp?
Solution
The low-frequency small-signal gain is,
Av =
1
(1.5)(2.5)(0.026)2(0.06+0.08)(0.06+0.08) = 20,126 V/V
The gain bandwidth is
GB =
100x10-9
2.5(0.026)(5x10-12) = 307,690 rps 49.0 kHz
The slew rate is
SR = (2)(307690)(2.5)(0.026) = 0.04 V/μs
The power dissipation is,
Pdiss = 3(0.7μA) =2.1μW
CMOS Analog Circuit Design © P.E. Allen - 2010

4. Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-7
Push-Pull Output Op Amp in Weak Inversion
First stage gain is,
Avo =
gm2
gm4 =
ID2n4Vt
ID4n2Vt =
ID2n4
ID4n2 1
Total gain is,
Avo =
gm1(S6/S4)
(gds6+gds7) =
(S6/S4)
(6+7)n1Vt
At room temperature (Vt = 0.0259V) and
for typical device lengths, gains of 60dB
can be obtained.
The GB is,
GB =
gm1
C
S6
S4 =
gm1b
C
M3 M4
M1 M2
+
VBias
-
M8
M9
vi2
where b is the current ratio between M4:M6 and M3:M8.
vou
VDD
M5
VSS
Cc
M6
M7
Fig. 7.4-2
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-8
Increasing the Gain of the Previous Op Amp
1.) Can reduce the currents in M3
and M4 and introduce gain in the
current mirrors.
2.) Use a cascode output stage
(can’t use self-biased cascode,
currents are too low).
Av =
gm1+gm2
2 Rout
=
gm1
gds6gds10
gm10 +
gds7gds11
gm11
=
I5
2nnVt
I72n2
I7
nnVt
I72p2
I7
npVt
+
=
I5
2I7
M8
M9
vi1
M3 M4
M1 M2
+
M5
VBias
-
1
vi2
2(nnn
nnVt
I5
2+npp
2)
M6
M10
VT+2VON
M13
M14
+
-
M12 M11
M7
vout
VDD
VSS
Cc
M15
+
VT+2VON
-
Fig. 7.4-3A
Can easily achieve gains greater than 80dB with power dissipation of less than 1μW.
CMOS Analog Circuit Design © P.E. Allen - 2010

5. Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-9
Increasing the Output Current for Weak Inversion Operation
A significant disadvantage of the weak inversion is that very small currents are available
to drive output capacitance so the slew rate becomes very small.
Dynamically biased differential amplifier input stage:
Note that the sinking current for M1 and M2 is
Isink = I5 + A(i2-i1) + A(i1-i2) where (i2-i1) and (i1-i2) are only positive or zero.
If vi1vi2, then i2i1 and the sinking current is increased by A(i2-i1).
If vi2vi1, then i1i2 and the sinking current is increased by A(i1-i2).
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-10
Dynamically Biased Differential Amplifier - Continued
How much output current is available from this circuit if there is no current gain from the
input to output stage?
Assume transistors M18 through M21 are equal to M3 and M4 and that transistors M22
through M27 are all equal.
Let
W28
L28 = A

7. W26
L26 and
W29
L29 = A

9. W27
L27
The output current available can be found by assuming that vin = vi1-vi2 0.
i1 + i2 = I5 + A(i2-i1)
The ratio of i2 to i1 can be expressed as
i2
i1 = exp

11. vin
nVt
If the output current is iOUT = b(i2-i1) then combining the above two equations gives,
iOUT =
bI5
exp

13. vin
nVt
-1
(1+A)-(A-1)exp

15. vin
nVt
iOUT = when A = 2.16 and
vin
nVt
= 1
where b corresponds to any current gain through current mirrors (M6-M4 and M8-M3).
CMOS Analog Circuit Design © P.E. Allen - 2010

16. Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-11
Overdrive of the Dynamically Biased Differential Amplifier
The enhanced output current is
accomplished by the use of positive
feedback (M28-M2-M19-M28).
The loop gain is,
LG =
gm28
gm4
gm19
gm26 = A
gm19
gm4 = A
Note that as the output current
increases, the transistors leave the weak
inversion region and the above analysis
is no longer valid.
A = 1.5
A = 1
A = 0.3
A = 0
A = 2
IOUT
I5
2
1
0
0 1 2
vIN nVt Fig. 7.4-5
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-12
Increasing the Output Current for Strong Inversion Operation
An interesting technique is to bias the output transistor of a current mirror in the active
region and then during large overdrive cause the output transistor to become saturated
causing a significant current gain.
Illustration:
i1 i2
M1 M2
+
Vds2
-
VGS
i2 for W2/L2 = 5.3(W1/L1)
Volts
i2 for W2/L2 = W1/L1
VGS
0.1Vds2(sat) Vds1(sat)=Vds2(sat)
070507-02
530μA
Current
100μA
+
VGS -
CMOS Analog Circuit Design © P.E. Allen - 2010

17. Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-13
Example 290-2 Current Mirror with M2 operating in the Active Region
Assume that M2 has a voltage across the drain-source of 0.1Vds(sat). Design the
W2/L2 ratio so that I1 = I2 = 100μA if W1/L1 = 10. Find the value of I2 if M2 is
saturated.
Solution
Using the value of KN’ = 120μA/V2, we find that the saturation voltage of M2 is
Vds1(sat) =
2I1
KN’(W2/L2) =
200
120·10 = 0.408V
Now using the active equation of M2, we set I2 = 100μA and solve for W2/L2.
100μA = KN’(W2/L2)[Vds1(sat)·Vds2 - 0.5Vds22]
= 120μA/V2 (W2/L2)[0.408·0.0408 - 0.5·0.04082]V2 = 1.898x106(W2/L2)
Thus,
100 =1.898(W2/L2)
W2
L2 = 52.7 53
Now if M2 should become saturated, the value of the output current of the mirror with
100μA input would be 530μA or a boosting of 5.3 times I1.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-14
Implementation of the Current Mirror Boosting Concept
VDD
i1
M8
M7
M17
M18
M21 M22
vi1 vi2
M1M2
M29 M30
ki2
vo1 vo2
M27 M28
M3 M4
i1 i2 i1 i2
M9
M13
ki1
M10
M14
ki2 ki1
M25 M26
i2
+
M23 M24
VSS
i2
i1
M5
M6
M16
M12
M15
M11
M19
M20
Fig.7.4-7
VBias
-
k = overdrive factor of the current mirror
CMOS Analog Circuit Design © P.E. Allen - 2010

18. Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-15
A Better Way to Achieve the Current Mirror Boosting
It was found that when the current mirror boosting idea illustrated on the previous slide
was used that when the current increased through the cascode device (M16) that VGS16
increased limiting the increase of VDS12. This can be overcome by the following circuit.
M3
VDD
IB
M5 M4
iin+IB iin
1/1 1/1
M1 M2
kiin
1/1
50/1
210/1
Fig. 7.4-7A
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-16
REVIEW OF MOSFET NOISE MODELING AND ANALYSIS
Transistor Noise Sources (Low-Frequency)
Drain current model:
i 2
n1
D
G
M1 M1
S
D
G
S
M1 is
noiseless
M1 is
noisy
Fig. 7.5-0A
i
2n
=
(KF)ID
fCoxL2 or i
8kTgm
3 +
2n
=
(KF)ID
fCoxL2 if vBS 0
8kTgm(1+)
3 +
Recall that =
gmbs
gm
Gate voltage model assuming common source operation:
e
2n
=
i
2N
gm
2 =
8kT
3gm
+
KF
2fCoxWLK’ or
e
2n
=
8kT
3gm(1+)+
KF
2fCoxWLK’ if vBS 0
D
G
e2
n1
*
M1 M1
S
D
G
S
M1 is
noiseless
M1 is
noisy
Fig. 7.5-0C
CMOS Analog Circuit Design © P.E. Allen - 2010

19. Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-17
Minimization of Noise in Op Amps
1.) Maximize the signal gain as close to the input as possible. (As a consequence, only
the input stage will contribute to the noise of the op amp.)
2.) To minimize the 1/f noise:
a.) Use PMOS input transistors with appropriately selected dc currents and W and L
values.
b.) Use lateral BJTs to eliminate the 1/f noise.
c.) Use chopper stabilization to reduce the low-frequency noise.
Noise Analysis
1.) Insert a noise generator for each transistor that contributes to the noise. (Generally
ignore the current source transistor of source-coupled pairs.)
2.) Find the output noise voltage across an open-circuit or output noise current into a
short circuit.
3.) Reflect the total output noise back to the input resulting in the equivalent input noise
voltage.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-18
LOW NOISE OP AMPS
A Low-Noise, Two-Stage, Miller Op Amp
VDD
M5
M1 M2
M8 M9
M3 M4
M7
vout
M6
VSS
+
-
M10
M11
VBias
Cc
+
-
vin
I5
VSG7
e2
n2 e2
M1 M2
M8 M9
n1
e2
n7
*
*
*
e2
n8
*
e2
n9
*
VBias VBias
M7
e2
to
M6
Fig. 7.5-1
VDD
* *
M3 M4
VSS
e2
n3 e2
n4
e2
n6
*
The total output-noise voltage spectral density, e
2
to, is as follows where gm8(eff) 1/rds1,
e
2
to = gm6
2RII2
e
2
n6+e
2
n7+RI2

20. gm12e
2
n1+gm22e
2
n2+gm32e
2
n3+gm42e
2
n4+(e
2
n8/rds12)+(e
2
n9/rds22)
Divide by (gm1RIgm6RII)2 to get the eq. input-noise voltage spectral density, e
2
eq, as
e
2
eq =
e
2
to
(gm1gm6RIRII)2 =
2e
2
n6
2
n1
gm12RI2 + 2e
1+
gm3
gm1

22. 2

24. 2
e
n3
e
2
n1
+
e
2
n8
gm12rds12e
2
n1
2e
2
n1
1+

26. gm3
gm1
2

28. 2
e
n3
2
e
n1
where e 2
n6 = e 2
n7, e 2
n3 = e 2
n4, e 2
n1 = e 2
n2 and e 2
n8 = e 2
n9 and gm1RI is large.
CMOS Analog Circuit Design © P.E. Allen - 2010

29. Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-19
1/f Noise of a Two-Stage, Miller Op Amp
Consider the 1/f noise:
Therefore the noise generators are replaced by,
e
2
ni =
B
fWiLi
(V2/Hz) and i
2
ni =
2BK’Ii
fLi2 (A2/Hz)
Therefore, the approximate equivalent input-noise voltage spectral density is,
e
2
eq = 2e
2
n1
2 (V2/Hz)

31. 1+
KN’BN
KP’BP
L1
L3
Comments;
• Because we have selected PMOS input transistors, e
2
n1 has been minimized if we
choose W1L1 (W2L2) large.
• Make L1L3 to remove the influence of the second term in the brackets.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-20
Thermal Noise of a Two-Stage, Miller Op Amp
Let us focus next on the thermal noise:
The noise generators are replaced by,
e
2
ni
8kT
3gm (V2/Hz) and i
2
ni
8kTgm
3 (A2/Hz)
where the influence of the bulk has been ignored.
The approximate equivalent input-noise voltage spectral density is,
e
2
eq = 2e
2
n1

33. 1+
gm3
gm1
2
n3
e
e
2
2
n1
2
n1
= 2e
KNW3L1
KPW1L3 (V2/Hz)

34. 1+
Comments:
• The choices that reduce the 1/f noise also reduce the thermal noise.
Noise Corner:
Equating the equivalent input-noise voltage spectral density for the 1/f noise and the
thermal noise gives the noise corner, fc, as
fc =
3gmB
8kTWL
CMOS Analog Circuit Design © P.E. Allen - 2010

35. Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-21
Example 290-3 Design of A Two-Stage, Miller Op Amp for Low 1/f Noise
Use the model parameters of KN’ = 120μA/V2, KP’ = 25μA/V2, and Cox = 6fF/μm2
along with the value of KF = 4x10-28 F·A for NMOS and 0.5x10-28 F·A for PMOS and
design the previous op amp with ID5 = 100μA to minimize the 1/f noise. Calculate the
corresponding thermal noise and solve for the noise corner frequency. From this
information, estimate the rms noise in a frequency range of 1Hz to 100kHz. What is the
dynamic range of this op amp if the maximum signal is a 1V peak-to-peak sinusoid?
Solution
1.) The 1/f noise constants, BN and BP are calculated as follows.
BN =
KF
2CoxKN’ =
4x10-28F·A
2·60x10-4F/m2·120x10-6A/V2 = 1.33x10-22 (V·m)2
and
BP =
KF
2CoxKP’ =
0.5x10-28F·A
2·60x10-4F/m2·25x10-6A/V2 = 1.67x10-22 (V·m)2
2.) Now select the geometry of the various transistors that influence the noise
performance.
To keep e
2
n1 small, let W1 = 100μm and L1 = 1μm. Select W3 = 10μm and L3 =
20μm and letW8 and L8 be the same as W1 and L1 since they little influence on the
noise.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-22
Example 290-3 - Continued
Of course, M1 is matched with M2, M3 with M4, and M8 with M9.
e
2
n1 =
BP
fW1L1 =
1.67x10-22
f·100μm·1μm =
1.67x10-12
f (V2/Hz)
e
1.67x10-12
2
eq = 2x
f

37. 2 =
1+
120·1.33
25·1.67
2
1
20
3.33x10-12
f 1.0365 =
3.452x10-12
f (V2/Hz)
Note at 100Hz, the voltage noise in a 1Hz band is 3.45x10-14V2(rms) or 0.186μV(rms).
3.) The thermal noise at room temperature is
e
2
n1 =
8kT
3gm =
8·1.38x10-23·300
3·500x10-6 = 2.208x10-17 (V2/Hz)
which gives
e
2
eq = 2·2.208x10-17

39. 120·10·1
25·100·20 = 4.416x10-17·1.155= 5.093x10-17 (V2/Hz)
1+
2
eq to get
4.) The noise corner frequency is found by equating the two expressions for e
fc =
3.452x10-12
5.093x10-17 = 67.8kHz
This noise corner is indicative of the fact that the thermal noise is much less than the 1/f
noise.
CMOS Analog Circuit Design © P.E. Allen - 2010

40. Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-23
Example 290-1 - Continued
5.) To estimate the rms noise in the bandwidth from 1Hz to 100,000Hz, we will ignore
the thermal noise and consider only the 1/f noise. Performing the integration gives
105
3.452x10-12
Veq(rms)2 =
1
f df = 3.452x10-12[ln(100,000) - ln(1)] =
0.408x10-10 Vrms2 = 6.39 μVrms
The maximum signal in rms is 0.353V. Dividing this by 6.39μV gives 55,279 or 94.85dB
which is equivalent to more than 15 bits of resolution.
6.) Note that the design of the remainder of the op amp will have little influence on the
noise and is not included in this example.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-24
Low-Noise Op Amp using Lateral BJT’s at the Input
270
46.8 1.2
3.6
vout
VDD
M5
1296 3.6
3.6
vi2 vi1
Q1 Q2
M3 M4
480
18
VSS
M10 M11
Cc = 1pF
VSS
M7
M6
81.6
3.6
Rz = 300Ω
M8 M9
M12
M13M14
M15M16
480
18
58.2
7.2
R1
=34kΩ
D1
511
130
3.6
43.8
6.6
45.6
3.6
384
1.2
46.8
3.6
58.2
7.2
Fig. 7.5-6
10
8
6
4
2
0
Eq. input noise voltage of low-noise op amp
Voltage noise of lateral BJT at 170μA
10 100 1000 104 105
Frequency (Hz)
Noise (nV/ Hz)
Fig. 7.5-7
Experimental noise
performance:
CMOS Analog Circuit Design © P.E. Allen - 2010

41. Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-25
Summary of Experimental Performance for the Low-Noise Op Amp
Experimental Performance Value
Circuit area (1.2μm) 0.211 mm2
Supply Voltages ±2.5 V
Quiescent Current 2.1 mA
-3dB frequency (at a gain of 20.8 dB) 11.1 MHz
en at 1Hz 23.8 nV/ Hz
en (midband) 3.2 nV/ Hz
fc(en) 55 Hz
in at 1Hz 5.2 pA/ Hz
in (midband) 0.73 pA/ Hz
fc(in) 50 Hz
Input bias current 1.68 μA
Input offset current 14.0 nA
Input offset voltage 1.0 mV
CMRR(DC) 99.6 dB
PSRR+(DC) 67.6 dB
PSRR-(DC) 73.9 dB
Positive slew rate (60 pF, 10 k load) 39.0 V/μS
Negative slew rate (60 pF, 10 k load) 42.5 V/μS
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-26
Chopper-Stabilized Op Amps - Doubly Correlated Sampling (DCS)
Illustration of the use of chopper stabilization to remove the undesired signal, vu, form the
desired signal, vin.
Clock
+1
-1
t
= 1
T fc
Vin(f)
vin
f
vu
vB vC vout
Vu(f)
VA(f)
VB(f)
f
f
f
A1 A2
vA
0 fc 2fc 3fc
VC(f)
0 fc 2fc
3fc f
0 fc 2fc 3fc
Fig. 7.5-8
CMOS Analog Circuit Design © P.E. Allen - 2010

42. Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-27
Chopper-Stabilized Amplifier
VDD
M3M4
M1 M2
IBias
VSS
Chopper-stabilized Amplifier:
φ1
φ2
φ2
φ1
+
vin
-
VDD
M7M8
M5 M6
IBias
VSS
φ1
φ2
φ2
φ1
Circuit equivalent during φ1 phase:
vu1 vu2
+
A1
-
-
+
+
A2
-
-
+
vueq
Circuit equivalent during the φ2 phase:
vu2
A1
vueq = vu1 +
vu1 vu2
+
A1
-
-
+
+
A2
-
-
+
vueq
vueq = -vu1 +
vu2
A1
vu2 , vueq(aver) =
A1
Fig. 7.5-10
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-28
Example of a Two-Stage, Chopper-Stablized Op Amp
clkb
VDD
clkb
vnp
vnn
vnp
vnn
070507-03
clkb
clk
clk
VDD
clkb
vnn
vnp
vnn
vnp
VDD
M3 M4
clk clkb
clkb clk
clk
clk
M1 M2
Cc
VNB1 M5
M6
vout
M7
CMOS Analog Circuit Design © P.E. Allen - 2010

43. Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-29
Experimental Noise Response of the Chopper-Stabilized Amplifier
1000
100
10
Without chopper
With chopper
fc = 16kHz
With chopper fc = 128kHz
0 10 20 30 40 50
Frequency (kHz)
nV/ Hz
Fig. 7.5-11
Comments:
• The switches in the chopper-stabilized op amp introduce a thermal noise equal to kT/C
where k is Boltzmann’s constant, T is absolute temperature and C are capacitors
charged by the switches (parasitics in the case of the chopper-stabilized amplifier).
• Requires two-phase, non-overlapping clocks.
• Trade-off between the lowering of 1/f noise and the introduction of the kT/C noise.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-30
Improved Chopper Operation
In some cases, there are spurious signals in the neighborhood of the chopping
frequencies and its harmonics. These spurious signals such as common-mode
interference can mix to the baseband since the chopper amplifier is a time variant system
and therefore inherently nonlinear.
A bandpass filter centered at
the clock frequency can be used to
eliminate the aliasing of the
spurious signals and achieve a
reduction in effective offset.
Let =
fc-fo
fo
and be a given
fc
Output
Amplifier
vin vou
fo
Bandpass Filter
Input
Amplifier
Input
Modulator
Output
Modulator
041006-03
bound of . It can be shown† that
the achievable effective offset reduction, EOR, and the optimum Q for the bandpass filter,
Qopt, is
EOR =
8Q
(1+8Q2) , 1 and Qopt = 1/ 8
Improvements of 14dB reduction in effective offset are possible for = 0.8%.
† C. Menolfi and Q. Huang, “A Fully Integrated, Untrimmed CMOS Instrumentation Amplifier with Submicrovolt Offset,” IEEE J. of Solid-State
Circuits, vol. 34, no.8, March 1999, pp. 415-420.
CMOS Analog Circuit Design © P.E. Allen - 2010

44. Lecture 290 – Low Power and Low Noise Op Amps (3/28/10) Page 290-31
SUMMARY
• Operation of transistors for low power op amps is generally in weak inversion
• Boosting techniques are needed to get output sourcing and sinking currents that are
larger than that available during quiescent operation
• Be careful about using circuits at weak inversion, i.e. the self-biased cascode will cause
the resistor to be too large
• Primary sources of noise for CMOS circuits is thermal and 1/f
• Noise analysis:
1.) Insert a noise generator for each transistor that contributes to the noise.
(Generally ignore the current source transistor of source-coupled pairs.)
2.) Find the output noise voltage across an open-circuit or output noise current into a
short circuit.
3.) Reflect the total output noise back to the input resulting in the equivalent input
noise voltage.
• Noise is reduced in op amps by making the input stage gain as large as possible and
reducing the noise of this stage as much as possible.
• The input stage noise can be reduced by using lateral BJTs (particularily the 1/f noise)
• Doubly correlated sampling can transfer the noise at low frequencies to the clock
frequency (this technique is used to achieve low input offset voltage op amps).
CMOS Analog Circuit Design © P.E. Allen - 2010