34. architecture shifter1 of shift is
begin
reg : process(RST, CLK)
variable reg : bit_vector(0 to 7);
begin
if(RST = '1') then
reg := "00000000";
elsif(CLK = '1' and CLK'event) then
if(LOAD = '1') then reg := Data;
. else
reg := reg(1 to 7) & reg(0);
end if;
end if;
Q <= reg;
end process;
end shifter1;
Siva Nagendra