1. CAN CONTROLLER
IMPLEMENTATION
BY: HAGAI GAMLIEL AND SHAHAR GEFEN
SUPERVISOR: SHAHAR GINO

2. CAN YOU HEAR ME?

3. PROJECT GOALS
Design and Implementation of a CAN BUS
Controller for a reliable and robust
communication between different nodes
Using can bus protocol by BOSCH company

4. BACKGROUND AND MOTIVATION
• The can protocol implements
only layers 2 and 3 from
the 7 layers of the OSI model
for communication between
different nodes of a
communication network

5. BACKGROUND AND MOTIVATION
The Controller Area Network (CAN) is a serial
communication protocol used extensively for high-
speed embedded applications where noise immunity
and robustness is necessary.
• The CAN protocol uses a twisted pair cable to communicate
at speeds up to 1 Mbps (minimum 0.125Mbps).
It is highly fault-tolerant, making it ideal for safety-critical
applications.
• It is used for backbone network as well as the powertrain,

6. BACKGROUND AND MOTIVATION
• Asynchronous communication
• Any node can access the bus when the bus is quiet
• Non-destructive arbitration, 100% use of the
bandwidth without loss of data
• Automatic error detection, signaling and retries
• All nodes can send a message at any time, when
two nodes access the bus together, arbitration
decides who will continue.
• Bit stuffing is used to maintain synchronization.

7. HOW DOES A CAN BUS SYSTEM LOOKS LIKE?
COMMONLY USED IN CAR MOBILE SYSTEMS

8. DESIGN FLOW
BOSCH Can
specification
and AMBA
APB protocol
learning
Architecture
and design
implementati
on
in System
Verilog
Simulation,
Synthesis,
Layout

9. CAN SPECIFICATION
MESSAGE TRANSFER
• 4 different message-types (“frames”): Data, Remote, Error and Overload.
• Faulty nodes are automatically dropped from the bus, which prevents
any single node from bringing a network down, and ensures that
bandwidth is always available for critical message transmission (“Fault
Confinement”).
CAN
frame
DATA/REMO
TE
9

10. CAN SPECIFICATION
MESSAGE TRANSFER

11. CAN SPECIFICATION
ARBITRATION MECHANISM

12. AMBA APB PROTOCOL
Write transfer with wait stateRead transfer with wait state

13. ARCHITECTURE AND DESIGN
Node 1
CPU
CAN CONTROLER
CAN Transiver
CAN_H
CAN_L
Node 2
CPU
CAN CONTROLER
CAN Transiver
Node N
CPU
CAN CONTROLER
CAN Transiver
CAN BUS

14. ARCHITECTURE AND DESIGN
BLOCK DIAGRAM

15. ARCHITECTURE AND DESIGN
CAN CONTROLLER INTERFACE
• fclk – outer clock. Came from the cpu/mcu
which is connected to the controller.
• APB Interface – A transfer protocol for
communication between the cpu/mcu
and the controller (AMBA APB protocol).
• Interrupt – signal’s that one message
(or more) is received.
• Can Tx – the output signal which sent to the bus
• Can Rx – the input signal which came from the bus
paddr
pwrite
psel
penable
fclk
Rst_n
prdata[31:0]
pready
int
pwdata[31:0]
Can_tx
Can_rx
Canbus
InterruptAPBInterface
CAN Module

16. ARCHITECTURE AND DESIGN
BIT TIMING
The can bus uses asynchronous communication. Therefore, a
way to synchronize between the different nodes which connected
to the bus is needed.
Synchronization:
• Bit stuffing – If 5 consecutive bits with the same logic value
(‘0’ or ‘1’) occur in a row,
a bit with the opposite logic value (‘1’ or ‘0’) is sent.
• Hard synchronization – Every time that a data(or remote)
frame is sent, there is a transition from a sequence of logic
‘1’s to logic ‘0’, which represents ‘start of frame’ and used

17. ARCHITECTURE AND DESIGN
BIT TIMING – DEFINES THE BUS CLOCK
 
/ /Phase_Seg2 max(PhaseSeg1,InfoProcessingTime) time quanta
1
1 Prop_seg Phase_Seg1+Phase_Seg2
1
1 1 Prop_seg Phase_Seg1+Phase_Seg2
BRP
T
Q f
clk
T T
bus Q
f
clkf
bus BRP



   
 
  
   

18. ARCHITECTURE AND DESIGN
BIT TIMING
• Nominal bit rate is the number of bits per second transmitted in the
absence of resynchronization by an ideal transmitter.
• SYNC_SEG used to synchronize the various nodes on the bus.
• PROP_SEG used to compensate for the physical delay times within the
network.
• PHASE_SEG1, PHASE_SEG2 used to compensate for edge phase errors.
• Sample point is the point in time at which the bus level is read and
interpreted.
• Time quantum is a the fixed unit of time which can be derived from
the oscillator period.

19. SIMULATION
VERIFICATION TEST BENCH
• The simulation is built as two Can Controller
DUT units such as DUT2 is the stub and verifier
of DUT1.
• The APB stub is a functional unit that works by
the AMBA APB protocol and represents the
cpu/mcu that communicates with the controller.
The test-suit included a test for every internal
block, and final integration test for the whole
scheme of the controller.

20. SIMULATION
VERIFICATION TEST BENCH
• Reset Node1 and Node2
• Configure bit timing registers for both Nodes
• Write data to node1 and node 2 to be
transmitted ‘Data Frame’ simultaneously
on bus
initial begin
fclk=0;
rst_n1 = 0;
rst_n2 = 0;
#200
rst_n1 = 1;
rst_n2 = 1;
bit_time_config1;
bit_time_config2;
#10
apb_write_data_frame1;
apb_write_data_frame2;
#400000 $finish;
end

21. SIMULATION
WAVEFORM DIAGRAM
As can be seen, Node1 and
Node2 tried to send
a Data Frame to the bus.
Node1 has won the
arbitration stage and hence
continued to send his message
while Node2 stopped.
It can be seen that Node2 recieved the data which sent by Node1
and in the end of the frame the interrupt signal rose.

22. SYNTHESIS
TIMING REPORT – LONGEST PATH

23. SYNTHESIS
RESULTS SUMMARIES
The synthesis run with fclk=100Mhz which is the maximum frequency
of the controller.
synthesis result:
Total 9 cells
• Time
data required time 9.88 ns
data arrival time -9.79 ns
• Area
Total cell area: 95864.5
Total area: 136792.9
• Power
total power 68.0113 mW
0.5𝜇𝑚2
0.5𝜇𝑚2

24. LAYOUT
FLOORPLAN - PHYSICAL VIEW
• Tower 0.18u design kit
• Encounter 14.1
𝑇𝑜𝑡𝑎𝑙 𝑠𝑖𝑧𝑒 2074 × 2008 𝜇𝑚2

25. SUMMARY
•Explanation for the need of a good
communication controller.
•Can BOSCH and APB protocol specifications
•Architecture and design of the controller
•Test bench Simulation, Synthesis and Layout

26. THANK YOU FOR LISTENING