This document provides a summary of Ranan Fraer's experience and qualifications. He has over 18 years of experience in software engineering for electronic design automation technologies at Intel, specializing in pre-silicon validation and power-performance analysis from circuit to system levels. He has expertise in formal verification, dynamic verification, transaction-level modeling, and microarchitectural performance analysis.

1. RANAN FRAER
Tel: 054-7613529
E-mail: ranan.fraer@gmail.com
Eder str. 60, apt. 5, Haifa
SUMMARY
Senior SW Engineer with 18 years of experience in R&D of EDA technologies, and their deployment to Intel
designs. Expert in pre-silicon validation, from formal/dynamic verification at IP level, to virtual platforms for
HW/SW co-validation at SOC level. Additional expertise in power-performance analysis and optimization from
circuit to micro-architectural level.
KEY SKILLS
 Solve challenging problems by reduction to logic analysis, graphs and optimization problems. Implement and
fine-tune algorithms on top of existing packages, such as SAT solvers or formal verification engines.
 Software design and implementation of large-scale projects. Use a variety of programming paradigms from
object-oriented (C++) to functional (ML, Lisp) and scripting (Python, Tcl).
 Define and execute validation strategies for HW-SW co-validation. Hands-on experience with VCS, DVE,
Verdi, System Verilog Testbench, OVM, and Simics virtual platforms.
 Apply transaction/event models to raise the abstraction level of validation or power-performance analysis.
Hands-on experience with System C for performance modeling and functional abstraction.
 Experience with theorem provers (Coq, HOL, PVS) and formal methods (B, Z) during my graduate studies
 Technical leadership: ability to drive pathfinding projects, partner with industry and academia and mentor
junior colleagues.
PROFESSIONAL EXPERIENCE
1997-2016: Senior CAD Engineer at Intel Israel, Design Technologies and Solutions. List of major projects below.
2013 – 2016 HW/SW co-validation on pre-silicon platforms
Hybrid Simics-Vcs co-simulation flow connecting virtual platforms to the RTL validation environment. Enabled to
drive HW validation by the actual SW (firmware or BIOS), rather than by synthetic tests. More generally, enabled
reuse of post-silicon test content in pre-silicon validation. Applied to validation of Power Management, one of the
most complex protocols in Intel SOCs.
Scenario-driven specification and validation of HW/SW protocols, based on a visual formalism, iPave. The
specification is checked for compliance against simulation traces from either HW or SW environments. Applied
to validate a new hardware/firmware feature in Intel’s GPU.
2012 – 2013 Transaction-level validation for System C
Defined a transaction-level methodology for validating SystemC models. Implemented a new toolset of trackers,
checkers and coverage at transaction-level. Deployed to Intel’s GPU as part of a new design flow for high-level
synthesis from System C to Verilog. Trained and mentored validators from different design blocks.
2008 – 2011 Power and performance analysis at micro-architectural level
Developed tools to analyze CPU workloads based on a performance model. Used by architects to explore new
features, compare architectures and validate the performance model against RTL. Applied data mining to extract
essential indicators from very long workloads. Deployed to CPU architecture teams.
2004 – 2008 RTL power analysis and optimizations
Developed Dare, a state-of-the art tool for RTL power analysis and optimizations, with power savings estimated
via RTL-SCH mapping. The clock gating advisor employed sequential analysis and a SAT solver, to identify and
propagate don’t care conditions. Deployed successfully on all the lead CPU projects.
2003 – 2004 Assertion based verification

2. Developed Foresight, an ABV (Assertion Based Verification) flow. Foresight targeted Formal Verification at unit-
level by running in parallel thousands of assertions with automatic pruning heuristics. Deployed successfully to
non-expert users in CPU and chipset validation.
2000 – 2003 SAT based model checking
Developed Thunder, a SAT-based bounded model checker. It had full support for Intel’s property language, and
advanced optimizations for pre-processing SAT formulas. Thunder offered a huge leap in capacity and ease of
usage. Leveraged it to drive the use of Formal Verification to additional CPU projects and also to chipset projects.
1997-2000 BDD based model checking
Developed Forecast, a BDD-based symbolic model checker. Forecast replaced and outperformed an existing
model checker. Implemented heuristics for partitioning the state space, and a semi-exhaustive mode for bug
hunting. Deployed to the major CPU projects in Intel for Formal Verification of RTL blocks in pre-silicon validation.
EDUCATION
Ph.D. in Computer Science, INRIA (INRIA is the leading research lab in computer science in France)
Research Topic – “Analysis of Programs Annotated by Assertions”
Supervisor: Yves Bertot
M.Sc. in Computer Science, Ecole Normale Superieure de Lyon (ENS is one of the best universities in France)
Research Topic –”Reasoning with Executable Specifications”
Supervisors: Yves Bertot
B.Sc. in Computer Science, University “Alexandru Ioan Cuza” in Jassy, Romania
PUBLICATIONS AND PATENTS
Authored 1 book chapter and 14 refereed papers published in leading scientific conferences.
Inventor of 2 granted patents.
ACADEMIC ACTIVITIES
Teaching Assistant for the “Formal Verification” course at the Haifa University
Teaching Assistant for the “SAT Solvers” course at Technion- Israel Institute of Technology
Served in the Program Committees of the “Bounded Model Checking” workshop and the B Conference.
INDUSTRIAL ACTIVITIES
Accelera SystemC Verification Working Group 2013-2014
Si2 Power Format Working Group 2006-2007