Antony Lenat Raja S Resume

Resume S. Antony Lenat Raja
Principal Hardware Engineer
Total years of Experience: 14 + Years
+91-9962055398
lenatraja.antony@gmail.com
EXPERIENCE SUMMARY
14+ Years of experience in VLSI ASIC Logic Digital Design, RTL Coding, Functional Verification, Logic
Synthesis, Static Timing Analysis, Gate Level simulation, SOC Verification, FPGA Functional Verification Lead
and worked on projects in RISC Processor, UMTS MODEM Core, PIC24 Microcontroller, Multi-media SOC,
Graphic Chip, Fibre Channel Controller and Westrace MK2 I/OModule (RAIL Domain) for clients such as Invensys,
Siemens,Nazomi Communications,Brilliance Semiconductor, T-System,Uniwide Technology,QUALCOMM BDC and
Microchip TechnologyDesign. Worked for P50 SOC Verification on-site project proposal, delivery and sign-off in
Electron International Organization, Moscow.
1 QUALIFICATIONS
Qualification Issued by Date
Bachelors ofElectronics and Communication
Engineering
Mepco Schlenk Engineering College/
Madurai Kamaraj University,Sivakasi,Tamil
Nadu,India
2000
2 TECHNICAL SKILLS
Skills
Hardware / Platforms Windows 98/NT/2000/XP, UNIX, LINUX
Domain/Technology P50 RISC Processor, AHB/AXI, ADC/DAC, PMP, PIC24
Microcontroller Product, HSUPA, HSDPA, UMTS MSM6280
Core, UMTS MSM7200 Core, JA208 multi-media SOC, Fibre
Channel Controller
Programming Language
VHDL, Verilog, i860 Assembly, Vera, OOPS,OVA, SVA, QVM,
System Verilog, UVM
Packages/Tools ModelsimXE, CadenceNC VHDL, Aldec Active VHDL, Verdi,
Synopsys Vss Simulator, Spyglass, ALINT, Synopsys Design
Compiler, FPGA Compiler, Leonardo Spectrum, Primetime,
Formality,Mentor Graphics IC Station,Mentor Graphics Calibre,
Mentor Graphics Xcalibre
Scripting Languages TCL/TCK, PERL
3 OTHER TRAINING
Training Course Provider Year
Innovation Digital Thinking, Digitally Cognizant
Boot Camp, Workshop on Principles of Design
Thinking, Digital 101 Certified e-learning
program, CMMI High Maturity Practices, Client
Cognizant Technology Solution, Chennai 2016

+91-9962055398
Interfacing Skills,Agile Leadership,DeliveryRisk
Management
Mentor U2U Functional Verification Technical
Conference
Mentor Graphics, Bangalore 2015,2016
SUNG VLSI ASIC Technical Training Synopsys, Bangalore 2013
Questa SIM tool for Advance Verification training Cognizant Technology Solution, Chennai 2012
Configuration ManagementSynergy (1 day
Internal training),IBM Rational DOORS (1 day
Internal training)
Invensys DevelopmentCentre India Private
Limited,Hyderabad,India.
2009
Verdi Tool training (1-day Internal Course) Microchip TechnologyIndia Private Limited,
Bangalore, India.
2008
System Verilog Assertion (2 days Internal
Course)
Qualcomm Bangalore Design Centre
Private Limited,Bangalore, India.
2007
Qualcomm Verification Methodology(2 days
Internal Course)
Qualcomm Bangalore Design Centre
Private Limited,Bangalore, India.
2006
Vera Verification Language training (1 day
External Course)
Synopsys India Private Limited,Bangalore,
India. 2006
Chip Synthesis training (3 days External Course)
Synopsys India Private Limited,Bangalore,
India. 2003
PostGraduate Diploma in VLSI Digital Backend
Design Engineering (5 months Training Course)
Advanced Training Institute for Information
TechnologyPrivate Limited,Chennai, India.
2000
4 EMPLOYMENT HISTORY
Period Organisation Title and Responsibilities
Nov 2012 to till date CognizantTechnology
Solutions India Private
Limited,Chennai,India.
Worked on SOM110 (Signal Output Module) SOC
Verification, Safety Universal IO (SUIO) ASIC SOC
Verification and Tricon V11.2 System Verification &
Validation projects
Jan 2010 to May 2012 CognizantTechnology
Solutions India Private
Limited,Chennai,India.
Senior Hardware Development Engineer
Worked on SOM24 SOC Verification and Virtual Lamp
Output Module (VLOM) SOC Verification and
TRUE_FPGA module Integration projects
July 2009 to Dec 2009 Invensys Development
Centre, Hyderabad,India
Senior Hardware Design Engineer
Worked on VLOM SOC Verification project

+91-9962055398
Aug 2007 to Jan 2009 Microchip TechnologyIndia
Private Limited,Bangalore,
India.
Senior Design Engineer
Worked on PIC24 Microcontroller Products Functional
Verification, Validation and Gate Level Simulation
projects
June 2004 to July 2007 Qualcomm Bangalore
Design Centre Private
Limited,Bangalore, India.
Engineer
Worked on UMTS Modem SOC Verification projects,
JA208 Multimedia SOC, Picasso Graphic Chip Logic
Synthesis and STA projects
Jan 2001 to May 2004 U&I System Design
Limited,Bangalore,India
Member Technical ASIC
Worked on P50 SOC verification, Synthesis and Gate
level simulation project
Worked on Fibre Channel Controller Design,
Functional verification, Synthesis and Gate level
simulation project
5 ROLE AND EXPERIENCE
Project Role Detail Responsibilities Experience
ASIC Front-End
Verification
Engineer
Project #1: SUIO ASIC TS3330 Verification - Cognizant Technology
Solutions
 Prepared test input stimulus .CSV file for ADC0_SETUP and
ADC1_SETUP registers for test execution in test environment
 Prepared different valid combinations of input stimulus for DAC and
VSTANDARD Registers for SPI Negative test cases
 Reviewed SUIO Behavioural Hardware Test Design Specification
 Prepared SUIO ASIC Rev B Test Report
Tools Used: IBM Rational DOORS 9.6
Language Used: VHDL
5 Months
System Verification
and Validation
Engineer
Project #2: Tricon V11.2 System Verification & Validation – Cognizant
Technology Solutions
 Perform Test Execution from test procedure. Perform various testing
(Integration, System, Regression)
 Hands on experience of configuration of Modbus Master Slave
Transmission Control Protocol/Serial communication testing,Peer to Peer
communication testing and Scan Rate and Key Switch of Triconex
Products
 Successful completionofTricon Communication Module (TCM) MODBUS
Software Test Description in Tricon V11.2 System during Formal V&V
4 Months

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Tools Used: PLC (Programmable Logic Controller), IBM Rational DOORS 9.6
FPGA Front-End
Technical
Verification Lead
and Project
Management
Project #3: SOM110 SOC Verification – Cognizant Technology Solutions
 Actively involved/updated SOM110 Work package. Developed SOM110
Verification Plan and approved by Client, provided guidance in the
resolution of technical issues in verification phases ofSOM110 Blocks from
inception to project completion and maintenance, Reviewing the RTL
code, Test specification and verification artefacts, interact with
customer regarding the update oftechnical queries/issues and update the
response to team.
 Lead the entire SOM110 team and assign task based on available work,
monitor the task and guiding the team to complete the assigned blocks
verification as per the schedule with quality. Assign tasks for all team
members and ensure the team to complete the tasks. Updating Metrics
submission every month for this Project
Project #4: SOM24 SOC Verification – Cognizant Technology Solutions
 Actively contributed as part of the leadership team for SOM24 Verification
team and developed SOM24 Verification Plan and approved by Client.
Provided training related on PLD Process, Westrace MK2 I/O Module
overview, verification process, verification methodology and
environment and assistance in accomplishment of team member goals
and objectives.
 Provided guidance in the resolution of technical issues in verification
phases of SOM24 I/O Module from inception to project completion and
maintenance.
 Given training on Digital and VHDL to all the Junior Engineer.
 Given training on PLD Process to all the Hardware Design and Verification
Team.
Tools Used: Aldec Active HDL 8.3, IBM Rational DOORS, SYNERGY
Language Used: VHDL
3 Years 10 Months
Senior FPGA
Front-End
Verification
Engineer
Project #5: VLOM SOC Verification - Cognizant Technology Solutions
 Preparation of Test Specification Document, Functional Verification
and Coverage analysis of TRUE_LED_CONTROL,TRUE_SPI,
TRUE_CC_COM, TRUE_INTER_FPGA, TRUE_DSP blocks using
CENELEC standard EN50129 and SIL4 Level in RAIL Industry
 Code review Analysis
 Development of verification methodology for TRUE_FPGA Design
 Interacted with Client and Developed PLD Coding standard document
for Verification
1 Year 6 months

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Project #6: LOM110 TRUE FPGA Black Box Verification - Cognizant
Technology Solutions
 Preparation of Test Specification Documentfor TRUE FPGA Module
 Functional Verification and Code Coverage of TRUE FPGA Module
Tools Used: Active VHDL, ALINT Linting tool, DOORS, SYNERGY
Language Used: VHDL
Senior ASIC Front-
End Design and
Verification
Engineer
Project #7: PIC24 Products Functional Verification and Gate Level
Simulation using ASIC – Microchip
PIC24FJ64GB004 Functional Verification
 RTL, Pregate/Postgate net list check using Spyglass
 PMP Module Functional verification
 Pregate/Postgate simulation using Verdi
 ADC Module Validation
 STA (Timing Analysis) analysed and all the timing violation removed
PIC24FJ64GA004 Functional Verification & PIC24J128GA010
Validation
 Using regression, all the test cases were verified and validated
PIC24FJ256GB110 Functional Verification and Gate Level Simulation
 Using regression, all the test cases were verified and validated
Tools Used: Modelsim, Verdi, Spyglass Linting tool
Language Used: Verilog
1 Year 5 Months

+91-9962055398
ASIC Front-End
Verification
Engineer
Project #8: UMTS MODEM SOC Verification using ASIC – Qualcomm
Griffin2 (MSM 70864) Chip Level Verification
 Develop QVM Regression setup and full chip verification for all MSM
modem blocks and coverage report generated and analysed
Apollo Unified Modem (MSM7600) Chip Level Verification
 Develop QVM Regression setup and full chip verification for Apollo-
modem CDMA/UMTS blocks and coverage report generated and
analysed
Unified Sample Server (MSM 70700) Block Verification
 Sample Server test plan creation, development of Verification
environment using QVM
 Using Regression, all the test cases verified and functional coverage
and code coverage report were generated and analysed
 Preparation of Sample Server Assertion Plan and OVA code
development and generation of assertion coverage
 Using Regression, all the test cases were verified. Assertion failures
were identified and fixed
UMTS Hummingbird (MSM6280) Modem Core Block Level Assertion
Verification
 Preparation of Sample Server, Athena Demback Blocks Assertion
plan, OVA code development and generation of assertion coverage
UMTS Athena (MSM7200) Modem Core Block Level Assertion Verification
 Preparation of EUL Modulator Assertion plan, OVA code
development and generation of assertion coverage
Phoenix EBI (External Bus Interface) Functional Verification
 Development of Verification environment, test case creation,
functional verification and coverage report generated and analysed
Tool Used: Modelsim Questa simulation tool,Virsim
Language Used: VHDL, Vera, OVA, QVM
2 Years 6 Months

+91-9962055398
ASIC Front-End
Design Engineer
Project #9: JA208 multi-media SOC Logic Synthesis and STA - Qualcomm
 Complete automation ofSynthesis & STA with Make file,DC/PERL scripts
maintained under CVS repository
 Hierarchical compilation with Bottom-up synthesis approach with time
budgeted and/or characterized constraints
 Compilationofnon-timingcritical modules for area and critical modules for
timing
 Optimization of 2 critical modules with different timing optimization
techniques
 Porting legacy, false and multi-cycle path constraints
 Development of chip-level IO constraints by looking at RTL and
specifications
 Max. Min and Typical case timing analysis for functional and test modes
for pre and post layout with SPEF annotated net lists.
Tool Used: Design Compiler,PrimeTime
Language Used: VHDL, TCL/TCK
Project #10: Picasso Graphic Chip STA - Qualcomm
 Complete automation of STA with DC/PERL scripts
 Max. Min and Typical case timing analysis for functional and test modes
Tool Used: PrimeTime
Scripting Language Used: PERL
7 Months

+91-9962055398
ASIC Front-End
Design and
Verification
Engineer
Project #11: P50 SOC Verification, Logic Synthesis and Gate Level
Simulation using ASIC – U&I System Design
 Executed and delivered the complete P50 RISC Core Project in
customer location and ittargeted and executed for 0.25-micron
technology for ASIC 5M Gate Design.
 Assembly code written and tested in assembler.
 Test plan and test case development for all the core instruction.
 The enhancement of self-checking full chip test bench verification
using VHDL and gate level simulation
 Logic synthesis, timing closure of P50 RISC core
 Reviewed the entire product of P50 RISC Core in customer location
and provided feedback regarding the entire life cycle of this productas
per verification and design implementation perspective.
Tools Used: ModelsimXE,Synopsys Vss simulation tools,Synopsys Design
Compiler
Language Used: VHDL, i860 Assembly
Project #12: Loop Port State Machine (LPSM) for Fibre Channel Controller
Design and Verification using FPGA – U&I System Design
 Architecture design of data paths and control state machine for fibre
channel controller.
 RTL coding, functional verification, logic synthesis and gate level
simulation for LPSM.
 Development of top-level verification environment with TEXTIO (File)
approach for the test stimulus database.
Tools Used: Cadence NC VHDL simulation tool, FPGA Compiler
Language Used: VHDL
3 Years 5 months

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