Hi speed board design for signal integrity and Electromagnetic Compatibility PCB Design

1. High Speed Board Design
for Signal Integrity
Introduction
90 minutes 2021
Written & Lectured by
Shalom Shlomi Zigdon
SHALOM-SHLOMI-ZIGDON@ITECH-ICOLLEGE.COM
Board Design Academy - Israel & Silicon Valley, Santa Clara, Ca, USA

2. PCB Layout>PCB Assembly> Product
By Henrik B. Christophersen

3. The Time is Changing my friend [Bob Dylan]
•
1
3
Lossyline
Transmission
Line
Lossless
Transmission
Line
SHORT TYPE
Super
Distributed
Distributed Lumped System
Maxwell
Telegraph
Maxwell Ohm & Kirchhoff Laws
Impedance &
Resistance
Impedance Resistance performance
E.M. Waves
Dielectric Field
E.M. Waves Voltage data

4. 4
The AC of the DC
•The Signal has the potential to be an Electromagnetic Field
•propagating
•between the Conductor and the Reference Planes
During Switching time [tR, tF]
dV/dt
Causes
Electric Field =Capacitance
dI/dt
Causes
Magnetic Field =Inductance

5. TEL = Transmission Electrical Length
Saturation Length = Spatial Extent
CRITICAL LENGTH = ½ TEL = tR [in nanoSecond] x 3 [in
inch]
Length of Switching Signal = RiseTime x Vsignal
= tR [in nanoSecond] x 6 [in inch]
5

6. Identify and Catch the Snakes
In your electronic schematic
HyperLynx v9.1
GND
VCC
The Imaginary part of your Schematic Design are the
Real life in your PCB
6

7. Transmission Line Parameters
7
Capacitance between conductors, C (F/m)
Inductance of conductor loop, L (H/m)
Resistance of conductors (conductor loss), R (Ω/m)
Shunt conductance (dielectric loss), G (S/m)
)
(
)
(
0
C
j
G
L
j
R
Z






8. 8
transmitter receiver
DRIVER
RECEIVER
Reference Plane
Single-Ended Signal
RETURN CURRENT LOOP AREA
Signal Integrity Problem #1: Signal Quality
Z missmatching >>Reflection >> Overshoot>>
Ringing>> Distortion >> MulFunctiom

9. CROSSTALK = E.M. Coupling
among Conductors
9
L
Inductive
coupling
Capacitive
coupling
Active / aggressor
Quiet / victim
Signal Integrity Problem #2: Cross Talk

10. Signal Integrity Problem #3: Rail collapse
in the power distribution system (PDS)
10

11. 11
Signal Integrity Problem #4: EMI
Electro Magnetic Interference

12. Typical embedded system block diagram
12

13. • Self aggression noise
• From VRM on VRM From Vcc on Vcc From Vdd on Vdd
• From signals on signals
• “Pollution” of the board/pkg interconnects
• From VRM From I/O From core From signals
• Mutual aggressors: cross talk coupling from the PDN
• To VRM To I/O To core To signals
13

14. MIND
THE
GAP
14
What cause our Project to stuck?
THE GAP

15. Engineering Intuition development
High Impedance Low Impedance
15

16. Lossy Lines
Toll way Highway
Lossless Lines
Pay for the gas
+ for the air/Dielectric surrounding you
Pay for the gas
Resistance Losses Skin Effect + Dielectric Losses Loss Tangent
16

17. EDDY CURRENTS
17
Skin Effect
‫ברמת‬
DC
LOW AC
HIGH SPEED AC

18. 18
requency impedance
Low Capacitive
Self-Resonance Resistive
High Inductive

19. ESL & ESR 10uF 6.3 V
19

20. 20

21. Any loop Generates Radiation – “Antenna”
)
(
)
(
)
(
2
)
(
)
/
( *
*
3
.
1 2
meters
amps
cm
MHz
m
V
R
I
A
f
E 
Minimize the dielectric thickness
between Signal Layers and Power Planes
Hi-Speed Board Design for Signal & Power Integrity + PCB Design for EMC Compliance
current flows in a loop
There must be a return current
DRIVER RECEIVER
Reference Plane
Signal Conductor
A = Return Current
Loop Area
21

22. 22

23. HyperLynx v9.1
GND2
GND3
HyperLynx v9.1
GND
VCC
The Electromagnetic Field Territory
23

24. Fourier Transform
24

25. 25
Fourier composition of a sawtooth wave
Fourier composition of a square wave

26. DRIVER RECEIVER
DRIVER RECEIVER
DRIVER RECEIVER

27. CURRENT PATH of Microstrip [Top Layer]
Layer#2: Ground Plane
Rise Time: Low-to-High Transition
Vdd / Vcc
Vss / GND
Dielectric
Cin
Current Source: Bypass/Decoupling Capacitor
Return Current Path: GND / Vss Plane
Cin
27

28. Vdd / Vcc
Vss / GND
Dielectric
Cin
Current Source: Parasitic Capacitance
Return Current Path: GND / Vss Plane
Cin
CURRENT PATH of Microstrip [Top Layer]
Layer#2: Ground Plane
Fall Time: High-to-Low Transition
28

29. Vdd / Vcc
Vss / GND
Dielectric
Cin
Dielectric
Current Source: Bypass/Decoupling Capacitor & Parasitic Capacitance
Return Current Path: Power/Vcc/Vdd Plane & GND / Vss Plane
Cin
CURRENT PATH of Stripline Layer#4:
between Power/Ground Planes
Rise Time: Low-to-High Transition
29

30. Reflection from a HARD boundary
30
Reflection from a SOFT boundary

31. Discontinuities in the characteristic impedance
31
shunt capacitance
• series inductance

32. •
‫העומס‬ ‫ליד‬ ‫נגד‬ ‫כולל‬ ‫הסיגנל‬ ‫הולכת‬ ‫מסלול‬ ‫כאשר‬
•
‫לטרנסיברים‬
‫ל‬ ‫יחסית‬ ‫מאוד‬ ‫גבוה‬ ‫כניסה‬ ‫אימפדנס‬
-Zo
•
‫יתרונות‬
:
‫נגד‬ ‫בהוספת‬ ‫פשטות‬
,
‫רמת‬
-
‫מופחתת‬ ‫לא‬ ‫סיגנל‬
,
Tr
‫נשמר‬
•
‫חסרונות‬
:
‫גבוה‬ ‫דרייב‬ ‫זרם‬ ‫נדרש‬
Parallel Terminations
Zo
32
Rparallel = Z0

33. •
Rserial = Zo - Zdriver
•
‫המקור‬ ‫ליד‬ ‫נגד‬ ‫דרך‬ ‫הסיגנל‬ ‫הולכת‬ ‫מסלול‬ ‫כאשר‬
•
‫קימים‬
‫עם‬ ‫רכיבים‬
‫טרמינציה‬
‫טורית‬
built-in
•
‫יתרונות‬
:
‫פשטות‬
–
‫נגד‬ ‫הוספת‬
.
‫נמוך‬ ‫דרייבר‬ ‫זרם‬ ‫כאשר‬ ‫אפשרי‬
,
‫ויפחית‬ ‫פחות‬ ‫יקרין‬ ‫לכן‬ ‫זרם‬ ‫עומת‬ ‫מקטין‬
ground bounce
•
‫חסרונות‬
:
‫כאשר‬ ‫רק‬ ‫ישים‬
driver ZOUT <ZO
•
‫מאיט‬
‫זמן‬ ‫את‬
-
‫עלית‬
-
‫האות‬
Tr
‫קבוע‬ ‫עקב‬
-
‫הזמן‬
RC
[
‫יתרון‬
:
‫להפחתת‬ ‫תורם‬
crosstalk
]
•
‫בודד‬ ‫לעומס‬ ‫מתאים‬
single loads
Series Terminations
Zo
Rs
33
Vdrvr
V-Rs
Vrcvr
t=0 t=Tpd t=2Tpd
t=0+

34. •
‫זרם‬ ‫נדרש‬
-
‫יותר‬ ‫נמוך‬ ‫דרייבר‬
•
‫סימטרית‬ ‫לתפקד‬ ‫לדרייבר‬ ‫עוזר‬
•
‫ל‬ ‫מתאים‬
3-state
Pull-up / Pull-down [thevenin] Termination
2
1
1
t
t
t
CC
T
R
R
R
V
V


Zo
TTL FAST R=2Zo
ECL = 1.6Zo[up] + 2.6Zo[down]
34
Rp = 2 Zo
Rp = 2 Zo

35. AC Termination
• CMOS
• No dc power consumption.
• C should be small to avoid high power consumption, but not
too small to allow sink current
35
C = 3 tR / Zo+R

36. BOTH ENDS TERMINATION
Bi-Directional DATA
36

37. Electromagnetic Interference (EMI) Coupling Path
•mechanisms:
1. Conduction - electric current
•2. Radiation - electromagnetic field
•3. Inductive Coupling - magnetic field
•4. Capacitive Coupling - electric field
37
EMI is produced by a source emitter and
is detected by a susceptible victim via a
coupling path

38. 38

39. EMC CHAMBER = FARADAY CAGE
39

40. 40
‫כלובי‬ ‫יצירת‬
‫פאראדיי‬
‫החוצה‬ ‫קרינה‬ ‫למניעת‬
/
‫פנימה‬
‫רועשות‬ ‫סיגנלים‬ ‫קבוצות‬ ‫בין‬ ‫צימוד‬ ‫מניעת‬
/
‫רגישות‬
•
‫גבוהים‬ ‫זרמים‬ ‫עם‬ ‫אנאלוגיים‬
•
SENSITIVE ANALOG SIGNALS
•
‫ווידאו‬
‫אאודיו‬
•
‫מימשקי‬
I/O Input/Output
•
‫שעונים‬
CLOCKS
‫שונים‬ ‫בתדרים‬
•
‫מ‬ ‫גבוהים‬ ‫תדרים‬ ‫דיגיטליים‬ ‫סיגנלים‬
-
3MHZ
•
DATA/Address
‫תדר‬ ‫לפי‬
Hz
‫קצב‬ ‫או‬
bps
•
Ethernet
•
USB
PCI-x
•
‫אספקות‬
‫למעגל‬ ‫מחוץ‬ ‫ממקור‬ ‫מתח‬
12 Layers PCB

41. PLAN - 2 Oz
PLAN - 2 Oz
PLAN - 1 Oz
PLAN - 1 Oz
SIGNALS - 1 Oz
SIGNALS - 1/2 Oz
SIGNALS - 1/2 Oz
SIGNALS - 1 Oz
41
Keep Copper Balance ‫מקו‬ ‫ומרחקו‬ ‫הנחושת‬ ‫עמס‬ ‫איזון‬ ‫שמירת‬
‫האמצע‬
BGA Balls to Pads ‫הפרנט‬ ‫קשתיות‬ ‫למניעת‬
–
‫לנתק‬ ‫יגרום‬
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
‫צעד‬
1
–
‫השכבות‬ ‫חתך‬ ‫אמצע‬ ‫קו‬ ‫שרטט‬

42. Power Splitted – 2 oz
SIGNALS – V-1/2
Oz
Faraday Cages
The wrong & right methods
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
GND - 2 Oz
GND - 1 Oz
PLAN - 2 Oz
PLAN - 2 Oz
PLAN - 2 Oz
GND - 2 Oz
Power Splitted – 2 oz
GND - 1 Oz
SIGNALS – H-1/2 Oz
SIGNALS-H - 1/2 Oz
SIGNALS –V - 1/2 Oz
GND - 1 Oz
GND - 1 Oz
TOP – ½+1 Oz
BOTTOM – ½+1 Oz
SIGNALS-H - 1/2 Oz
SIGNALS-H - 1/2 Oz
SIGNALS –V - 1/2 Oz
SIGNALS –V - 1/2 Oz
PLAN - 2 Oz
Short
Pa
d
Short
Pa
d
PLAN - 2 Oz
PLAN - 2 Oz
SIGNALS-H
SIGNALS –V
DON’T
42