3. 3
Low-Noise Amplifier
• First gain stage in receiver
– Amplify weak signal
• Significant impact on noise performance
– Dominate input-referred noise of front end
• Impedance matching
– Efficient power transfer
– Better noise performance
– Stable circuit
LNA
subsequent
LNAfrontend
G
NF
NFNF
1
4. 4
LNA Design Consideration
• Noise performance
• Power transfer
• Impedance matching
• Power consumption
• Bandwidth
• Stability
• Linearity
5. 5
Noise Figure
• Definition
• As a function of device
G: Power gain of the device
outout
inin
out
in
NS
NS
SNR
SNR
NF
source
sourcedevice
NG
NGN
NF
6. 6
NF of Cascaded Stages
• Overall NF dominated by NF1
[1] F. Friis, “Noise Figure of Radio Receivers,”
Proc. IRE, Vol. 32, pp.419-422, July 1944.
Sin/Nin
G1, N1,
NF1
Gi, Ni,
NFi
GK, NK,
NFK
Sout/Nout
12121
3
1
2
1
111
11
K
K
...GGG
NF
...
GG
NF
G
NF
NFNF
7. 7
Simple Model of Noise in MOSFET
fWLC
k
fV
ox
g )(2
• Flicker noise
– Dominant at low frequency
• Thermal noise
– g: empirical constant
2/3 for long channel
much larger for short channel
– PMOS has less thermal noise
• Input-inferred noise
md gkTfI g4)(2
Vg
Id
Vi
fWLC
k
g
kTfV
oxm
i
g
4)(2
9. 9
Power Transfer and Impedance Matching
L
LLss
s
del R
jXRjXR
V
P
2
s
ss
XXRRL
R
VV
PP
LsLs
4
*
0,max
• Power delivered to load
• Maxim available power
Rs
Vs
jXs jXL
RL
I V
• Impedance matching
– Load and source impedances conjugate pair
– Real part matched to 50 ohm
13. 13
S-Parameters
• Parameters for two-port system analysis
• Suitable for distributive elements
• Inputs and outputs expressed in powers
– Transmission coefficients
– Reflection coefficients
15. 15
S-Parameters
• S11 – input reflection coefficient with
the output matched
• S21 – forward transmission gain or
loss
• S12 – reverse transmission or
isolation
• S22 – output reflection coefficient with
the input matched012
2
22
012
1
12
021
2
21
021
1
11
a
a
a
a
a
b
S
a
b
S
a
b
S
a
b
S
17. 17
Stability Condition
• Necessary condition
where
• Stable iff
where
1
||2
||||||1
2112
22
11
2
22
SS
SS
K S
21122211 SSSSS
1|| 2
LLS
2
||||
||
2
22
2
11
2112
SS
SSL
18. 18
A First LNA Example
• Assume
– No flicker noise
– ro = infinity
– Cgd = 0
– Reasonable for appropriate
bandwidth
• Effective transconductance
Rs
Vs
Vs
Rs 4kTRs
Vgs
gmVgs 4kTggm
ins
inm
s
o
meff
ZR
Zg
V
i
G
io
19. 19
Power Gain
• Voltage input
• Current output
2
22
2
22
2
2
*
*
1
)(1
1)(1
)(1
||
s
T
gss
m
gss
m
gss
gsm
ins
inm
meff
ss
oo
RCR
g
CRj
g
CjR
Cjg
ZR
Zg
G
VV
ii
G
20. 20
Noise Figure Calculation
• Power ratio @ output
– Device noise + input-induced noise
– Input-induced noise
2
2
222
22
2
)/(
1
)1(1
)(1
4
4
1
gsm
ms
ms
gss
ms
gss
m
s
m
in
indevice
Cg
gR
gR
CR
gR
CR
g
kTR
gkT
NG
NGN
NF
g
g
g
g
gs
m
T
C
g
21. 21
Unity Current Gain Frequency
Device ioutiin
1
ω
ω
Tin
Tout
i
in
out
i
i
i
A
i
i
A
T
0dB
fT
Ai
ffrequency
24. 24
T of NMOS and PMOS
• 0.25um CMOS Process*
[2] Tajinder Manku, “Microwave CMOS - Device Physics and Design,”
IEEE J. Solid-State Circuits, vol. 34, pp. 277 - 285, March 1999.
m
gdgs
m
T g
CC
g
1
)(
)(
21
11
T
T
jY
jY
Set:
Solve for T
25. 25
Noise Performance
• Low frequency
– Rsgm >> g ~ 1
– gm >> 1/50 @ Rs = 50 ohm
– Power consuming
• CMOS technology
– gm/ID lower than other tech
– T lower than other tech
2
2
1
T
ms
ms
gR
gR
NF
g
g
26. 26
Review of First Example
• No impedance matching
– Capacitive input impedance
– Output not matched
• Power transfer
– S11=(1-sRCgs)/(1+sRCgs)
– S21=2Rgm/(1+sRCgs), R=Rs=RL
• Power consumption
– High power for NF
– High power for S21
29. 29
Comparison with Previous Example
• Previous example
• Resistive-termination
2
22
11
T
sm
I
s
smI
s
Rg
R
R
RgR
R
NF
g
g
2
2
1
T
ms
ms
gR
gR
NF
g
g
Introduced by input
resistance Signal attenuated
30. 30
Summary - Resistive Termination
• Noise performance
– Low-frequency approximation
– Input matched Rs = RI = R
• Broadband input match
• Attenuate signal
• Introduce noise due to RI
• NF > 3 dB (best case)
Rg
NF
m
g4
2
31. 31
Series-Shunt Feedback
• Broadband matching
• Could be noisy
Rs
Vs
Ra
RF
RL
Vgs gmVgs
RF
iout
Ra
Cgs
Rs
Vs
RL
gsLFaaLm
gsaamLF
in
CRRRsRRg
CsRRgRR
R
)()(1
)1)((
))((1
)(
))((1
))(1(
asgsm
saFsFags
asgsm
sFam
out
RRsCg
RRRRRRsC
RRsCg
RRRg
R
33. 33
Input Impedance of CG Structure
• Input impedance
Yin=gm+sCgs
• Input-impedance matching
– Low frequency approximation
– Direct without passive components
1/gm=Rs=50 ohm
34. 34
Noise Performance of CG Structure
2
2
2222
222
2
41
)1(1
)()1(
4
4
1
T
gsssm
ms
gsssm
m
s
m
in
indevice
CRRg
gR
CRRg
g
kTR
gkT
NG
NGN
NF
gg
g
g
222
2
2
)()1( gsssm
m
eff
CRRg
g
GG
Signal attenuated
35. 35
Power Transfer of CG Structure
• Rs = RL = R = 50 ohm
• S11=0, S21=1 @ Low frequency
gss
gss
gsssm
gsssm
sin
sin
CsR
CsR
CsRRg
CsRRg
ZZ
ZZ
S
2
1
1*
11
gs
gsssm
mL
effL
sC
CsRRg
gR
GRS
2
2
1
2
221
36. 36
Summary – CG Structure
• Noise performance
– No extra resistive noise source
– Independent of power consumption
• Impedance matching
– Broadband input matching
– No passive components
• Power consumption
– gm=1/50
• Power transfer
– Independent of power consumption
37. 37
Inductor Degeneration Structure
Rs
Vs
Ls
Lg
Vgs gmVgs
iout
Cgs
Rs
Vs
Lg
Ls
Zin
Vin
iin
gs
sm
gs
sgin
s
gs
inmin
gs
ingin
sgsmin
gs
inginin
C
Lg
sC
LLsI
sL
sC
IgI
sC
IsLI
sLVgI
sC
IsLIV
1
)(
)
1
(
1
)(
1
Zin
38. 38
Input Matching for ID Structure
• Zin=Rs
– IM{Zin}=0
– RE{Zin}=Rs
gs
sm
gs
sgin
C
Lg
sC
LLsZ
1
)(
gssg CLL )(
12
0
s
gs
sm
R
C
Lg
Vgs gmVgs
iout
Cgs
Rs
Vs
LgLs
Zin
gmLs/Cgs
40. 40
Noise Factor of ID Structure
• Calculate NF at 0
22
22
2
)(1
)(
4
4
1
0
smgss
ms
smgss
m
s
m
in
indevice
LgCR
gR
LgCR
g
kTR
gkT
NG
NGN
NF
g
g
2222
2
2
)()](1[ smgsssggs
m
eff
LgCRLLC
g
GG
= 0 @ 0
41. 41
Input Quality Factor of ID Structure
CRRII
CII
powerLost
powerStored
Q
1
*
*
Cgs
Rs
Vs
LgLs
gmLs/Cgs
C
R
V
L
gsssmgss
gssmsgs
in
CRLgCR
CLgRCCR
Q
2
1
)(
1
)/(
11
I
42. 42
Noise Factor of ID Structure
2
22
1
1
)(1
0
inms
smgss
ms
QgR
LgCR
gR
NF
g
g
)(
1
smgss
in
LgCR
Q
• Increase power transfer
gmLs/Cgs = Rs
• Decrease NF
gmLs/Cgs = 0
• Conflict between
– Power transfer
– Noise performance
43. 43
Further Discussion on NF
sg
s
sggsms
sm
smgss
ms
LL
L
LLCgR
Lg
LgCR
gR
NF
g
g
g
4
1
)(
1)(4
1
)(1
2
22
0
• Frequency @ 0
2 ~= 1/Cgs/(Lg+Ls)
• Input impedance
matched to Rs
RsCgs=gmLs
• Suitable for hand
calculation and design
• Large Lg and small Ls
Tss RL
gsgs CLL 2
01
44. 44
Power Transfer of ID Structure
• Rs = RL = R = 50 ohm
• @
)()(1
)(1
)(1
)(1
2
2
2
2*
11
sggsgsssm
sggs
gsssmsggs
gsssmsggs
sin
sin
LLCsCRLgs
LLCs
CsRLsgLLCs
CsRLsgLLCs
ZZ
ZZ
S
)()(1
2
2 221
sggssmgss
Lm
Leff
LLCsLgCRs
Rg
RGS
)(
1
smgss
in
LgCR
Q
gssg CLL )(
12
0
s
LT
inLm
smgss
Lm
R
R
jQRgj
LgCRj
Rg
SS
00
2111 2
)(
2
;0
45. 45
Computing Av without S-Para
Rs
Vs
Ls
Lg
)(
2/1
22
;2
:matchimputandresonanceAt
0
00
0
oos
T
s
o
v
sTssgssmo
gsinmgsmossin
sin
YYR
j
V
V
A
RjVRCjVgI
CjIgVgIRVI
RZ
46. 46
Power Consumption
DDTgs
ox
DDD VVV
L
WC
VIP 2
)(
2
WLCC oxgs
3
2
)( Tgsoxm VV
L
W
Cg
2
22
2
3
Tgsox
gs
m
VV
L
W
C
C
Lg
gs
sm
s
C
Lg
R
s
gss
m
L
CR
g
)/1(3
1
)(3
1
3
)(333
32
0
222
2
0
22
2
0
2
22
2
2222
sgs
DDs
sg
DDT
DDgs
T
sg
DD
s
s
DDgs
s
s
DD
gs
m
LLL
VRL
LL
VL
VC
L
P
LL
V
L
RL
VC
L
RL
V
C
Lg
P
47. 47
Power Consumption
)/1(
1
32
0
22
sgs
s
LLL
RL
P
• Technology constant
– L: minimum feature size
– : mobility, avoid mobility saturation region
• Standard specification
– Rs: source impedance
– 0: carrier frequency
• Circuit parameter
– Lg, Ls: gate and source degeneration inductance
sg
s
LL
L
NF
g
4
1
0
48. 48
Summary of ID Structure
• Noise performance
– No resistive noise source
– Large Lg
• Impedance matching
– Matched at carrier frequency
– Applicable to wideband application, S11<-10dB
• Power transfer
– Narrowband
– Increase with gm
• Power consumption
– Large Lg
49. 49
Cascode
• Isolation to improve S12
@ high frequency
– Small range at Vd1
– Reduced feedback effect
of Cgd
• Improve noise
performance
Rs
Vs
Ls
Lg
Vbias
LL
M2
M1
Vd1
Vo
51. 51
LNA Design Example (1)
Rs
Vs
Ls
Lg
Ld
M2
M1
Lvdd
Vbias
M4
Lb1
Cb1
Tm
Cm
M3
Lgnd
Lout
Input
bias Off-chip
matching
[3] D. Shaeffer and T. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-
State Circuits, vol. 32, pp. 745 – 759, May 1997.
Lb2
Cb2 Vout
Output
bias
Vdd
52. 52
LNA Design Example (1)
Rs
Vs
Ls
Lg
Ld
M2
M1
Lvdd
Vbias
M4
Lb1
Cb1
Tm
Cm
M3
Lgnd
Lout
[3] D. Shaeffer and T. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-
State Circuits, vol. 32, pp. 745 – 759, May 1997.
Unwanted
parasitics
Supply
filtering
53. 53
Circuit Details
• Two-stage cascoded structure in 0.6 m
• First stage
– W1 = 403 m determined from NF
– Ls accurate value, bondwire inductance
– Ld = 7nH, resonating with cap at drain of M2
• Second
– 4.6 dB gain
– W3 = 200 m
61. 61
LNA Design Example (3)
• Objective is to design tunable RF LNA that
would:
– Operate over very wide frequency range with very fine
selectivity
– Achieve a good noise performance
– Have a good linearity performance
– Consume minimum power
62. 62
LNA Architecture
• The cascode architecture
provides a good input –
output isolation
• Transistor M2 isolates the
Miller capacitance
• Input Impedance is obtained
using the source
degeneration inductor Ls
• Gate inductor Lg sets the
resonant frequency
• The tuning granularity is
achieved by the output
matching network
VDD
LS
LG
M1
M2
LD
R2
R1
M3
Output to
Mixer
Input to LNA
Matching
Network
63. 63
Matching Network
• The output matching tuning
network is composed of a
varactor and an inductor.
• The LC network is used to
convert the load impedance
into the input impedance of
the subsequent stage.
• A well designed matching
network allows for a
maximum power transfer to
the load.
• By varying the DC voltage
applied to the varactor, the
output frequency is tuned to
a different frequency.
64. 64
Simulation Results - S11
• The input return loss
S11 is less than – 10dB
at a frequency range
between 1.4 GHz and
2GHz
Input return loss
65. 65
Simulation results - NF
• The noise figure is 1.8
dB at 1.4 GHz and rises
to 3.4 dB at 2 GHz.
Noise Figure
66. 66
Simulation Results - S22
S22 at 1.7725 GHzS22 at 1.77 GHz
• By controlling the voltage applied to the varactor the output frequency
is tuned by 2.5 MHz.
• The output return loss at 1.77 GHz is – 44.73 dB and the output return
loss at 1.7725 GHz – 45.69 dB.
67. 67
Simulation Results - S22
S22 at 1.9975 GHzS22 at 2 GHz
• The output return loss at 2 GHz is – 26.47 dB and the output return
loss at 1.9975 GHz – 26.6 dB.
69. 69
Simulation Results - Linearity
-1dB compression pointIIP3
• The third order input intercept is –3.16 dBm
• -1 dB compression point ( the output level at which the actual gain
departs from the theoretical gain) is –12 dBm
70. 70
From an earlier slide:
fWLC
k
fV
ox
g )(2
• Flicker noise
– Dominant at low frequency
• Thermal noise
– g: empirical constant
2/3 for long channel
much larger for short channel
– PMOS has less thermal noise
• Input-inferred noise
md gkTfI g4)(2
Vg
Id
Vi
fWLC
k
g
kTfV
oxm
i
g
4)(2
Not accurate for low voltage short channel devices
71. 71
Modifications
g is called excess noise factor
= 2/3 in long channel
= 2 to 3 (or higher!) in short
channel NMOS (less in PMOS)
gg m
dod
g
kTgkTfI 44)(2
Thermonoise
74. 74
Fliker noise
• Traps at channel/oxide interface randomly
capture/release carriers
– Parameterized by Kf and n
• Provided by fab (note n ≈ 1)
• Currently: Kf of PMOS << Kf of NMOS due to buried channel
– To minimize: want large area (high WL)
f
K
f
K
fI
fWLC
k
fV
f
n
f
d
ox
g
)(
)(
2
2
75. 75
Induced Gate Noise
• Fluctuating channel potential couples
capacitively into the gate terminal, causing a
noise gate current
– d is gate noise coefficient
• Typically assumed to be 2g
– Correlated to drain noise!
2
2
5
4
d
T
dong gkTi
76. 76
Input impedance
Set to be real and equal to source resistance:
real
gs
m
gs
gin
C
Lg
sC
LLssZ
deg
deg
1
)()(
gsg CLL )(
1
deg
2
0
s
gs
m
R
C
Lg
deg
77. 77
Output noise current
)14(21)( 222
QcgkTfI dddod g
Noise scaling factor:
)14(21
4
1 22
Qc dd
Where for 0.18 process
c=-j0.55, g=3, d=6, gdo=2gm,
d = 0.32
g
d
5do
m
d
g
g
s
g
gss R
LL
CR
Q
2
)(
2
1 deg0
0
78. 78
Noise factor
Noise factor scaling coefficient:
22
)14(21
2
dd
m
do
nf Qc
g
g
Q
K
g
22
)14(21
2
1 dd
m
do
T
o
Qc
g
g
Q
F
g
4
2
1)(41 022
00
Q
CR
gRNG
NGN
NF
T
gss
msin
indevice g
g
Compare:
80. 80
Example
• Assume Rs = 50 Ohms, Q = 2, fo = 1.8 GHz, ft = 47.8 GHz
• From
gss CR
Q
02
1
fF
eQR
C
s
gs 442
)2(98.12)50(2
1
2
1
0
nH
e
R
g
CR
L
T
s
m
gss
17.0
98.472
50
deg
nHL
C
L
CLL gs
g
gsg
5.17
1
)(
1
deg2
0deg
2
0
81. 81
Have We Chosen the Correct Bias Point?
IIP3 is also a function of Q
82. 82
If we choose Vgs=1V
• Idens = 175 A/m
• From Cgs = 442 fF, W=274m
• Ibias = IdensW = 48 mA, too large!
• Solution 1: lower Idens => lower power,
lower fT, lower IIP3
• Solution 2: lower W => lower power, lower
Cgs, higher Q, higher NF
84. 84
We now need to re-plot the Noise Factor scaling coefficient
- Also plot over a wider range of Q
Lower current density to 100
43.0
5
2
68.0
5
68.0
15.1
78.0
d
do
m
d
do
m
g
g
g
g
GHz8.422
9.2
78.0
fF
mS
C
g
gs
m
T
22
)14(21
2
1
1 dd
m
do
T
o
Qc
Qg
g
F g
86. 86
Recall
We previously chose Q = 2, let’s now choose Q = 6
- Cuts power dissipation by a factor of 3!
- New value of W is one third the old one
m
m
W
91
3
274
88. 88
Other architectures of LNAs
•Add output load to achieve voltage gain
•In practice, use cascode to boost gain
•Added benefit of removing Cgd effect
89. 89
Differential LNA
Value of Ldeg is now much better controlled
Much less sensitivity to noise from other circuits
But: Twice the power as the single-ended version
Requires differential input at the chip
90. 90
LNA Employing Current Re-Use
•PMOS is biased using a current mirror
•NMOS current adjusted to match the PMOS current
•Note: not clear how the matching network is achieving a 50 Ohm match
Perhaps parasitic bondwire inductance is degenerating the PMOS or
NMOS transistors?
91. 91
Combining inductive
degeneration and current reuse
Current reuse to save power
Larger area due to two degeneration
inductor if implemented on chip
NF: 2dB, Power gain: 17.5dB, IIP3: -
6dBm, Id: 8mA from 2.7V power supply
Can have differential version
F. Gatta, E. Sacchi, et al, “A 2-dB Noise Figure 900MHz Differential CMOS LNA,”
IEEE JSSC, Vol. 36, No. 10, Oct. 2001 pp. 1444-1452
92. 92
At DC, M1 and M2 are in cascode
At AC, M1 and M2 are in cascade
S of M2 is AC shorted
Gm of M1 and M2 are multiplied.
Same biasing current in M1 & M2
LIANG-HUI LI AND HUEY-RU CHUANG, MICROWAVE JOURNAL® from the February 2004 issue.
93. 93
bao
bmb
amamama
iii
vgi
vgvgvgi
3
3
3
3
2
21
•IM3 components in the drain
current of the main transistor has
the required information of its
nonlinearity
•Auxiliary circuit is used to tune the
magnitude and phase of IM3
components
•Addition of main and auxiliary
transistor currents results in
negligible IM3 components at
output
Sivakumar Ganesan, Edgar Sánchez-sinencio, And Jose Silva-martinez
IEEE Transactions On Microwave Theory And Techniques, Vol. 54, No. 12, December 2006
94. 94
MOS in weak inversion has speed problem
MOS transistor in weak inversion acts like bipolar
Bipolar available in TSMC 0.18 technology (not a parasitic BJT)
Why not using that bipolar transistor to improve linearity ?
95. 95
Inter-stage Inductor gain boost
Inter-stage inductor with
parasitic capacitance form
impedance match network between
input stage and cascoded stage
boost gain lower noise figure.
Input match condition will be
affected
99. 99
Step 1: Know your process
• A 0.18um CMOS Process
• Process related
– tox = 4.1e-9 m
– e = 3.9*(8.85e-12) F/m
– = 3.274e-2 m^2/V.s
– Vth = 0.52 V
• Noise related
– = gm/gdo
– d/g ~ 2
– g ~ 3
– c = -j0.55
101. 101
Insights:
• gdo increases all the way with current
density Iden
• gm saturates when Iden larger than
120A/m
– Velocity saturation, mobility degradation ----
short channel effects
– Low gm/current efficiency
– High linearity
• deviates from long channel value (1)
with large Iden
103. 103
Insights:
• fT increases with Vod when Vod is small and
saturates after Vod > 0.3V --- short channel
effects
• Cgs/W increases slowly after Vod > 0.2V
• fT begins to degrade when Vod > 0.8V
– gm saturates
– Cgs increases
• Should keep Vod ~0.2 to 0.4 V
104. 104
Obtain design guide plots
3-D plot for visual
inspection
2-D plots for
design reference
knf vs input Q and current density
105. 105
Design trade-offs
• For fixed Iden, increasing Q will reduce the
size of transistor thus reduce total power --
-- noise figure will become larger
• For fixed Q, reducing Iden will reduce
power, but will increase noise factor
• For large Iden, there is an optimal Q for
minimum noise factor, but power may be
too high
107. 107
Insights:
• MOS transistor IIP3 only, when embedded into
actual circuit:
– Input Q will degrade IIP3
– Non-linear memory effect will degrade IIP3
– Output non-linearity will degrade IIP3
• IIP3 is a very weak function of device size
• Generally, large overdrive means large IIP3
– But the relationship between IIP3 and gate overdrive
is not monotonic
– There is a local maxima around 0.1V overdrive
108. 108
Step 4: Estimate fT
Small current budget ( < 10mA )
does not allow large gate over drive :
Vod ~ 0.2 V ~ 0.4 V
fT ~ 40 ~ 44 GHz
115. 115
Comparison between targeted
specs and simulation results
Parameter Target Simulated
Noise Figure 1.6 dB 0.8 dB
Drain Current < 10mA 8 mA
Voltage gain 20 dB 21 dB
IIP3 -8 dBm -6.4 dBm
P1dB -20dbm
S11 -17 dB
Power supply 1.8 V 1.8 V
