High Speed Amplifier PCB Layout Techniques
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This training module introduces the effect of PCB layout for high speed performance
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High Speed Amplifier PCB Layout Techniques
- 9. Trace/Pad Capacitance d A K = relative dielectric constant A = area in cm 2 d = spacing between plates in cm
- 10. Trace/Pad Capacitance d A K = relative dielectric constant A = area in cm 2 d = spacing between plates in cm Example: Pad of SOIC L = 0.2cm W = 0.063cm K= 4.7 A = 0.0126cm 2 d = 0.073cm C = 0.072pF
- 11. Trace/Pad Capacitance d A K = relative dielectric constant A = area in cm 2 d = spacing between plates in cm Example: Pad of SOIC L = 0.2cm W = 0.063cm K= 4.7 A = 0.0126cm 2 d = 0.073cm C = 0.072pF Reduce Capacitance 1) Increase board thickness or layers 2) Reduce trace/pad area 3) Remove ground plane
- 12. Approximate Trace Inductance All dimensions are in mm
- 13. Approximate Trace Inductance Example L= 25.4mm W = .25mm H = .035mm (1oz copper) Strip Inductance = 28.8nH At 10MHz Z L = 1.86 a 3.6% error in a 50 system All dimensions are in mm
- 14. Approximate Trace Inductance Example L= 2.54cm =25.4mm W = .25mm H = .035mm (1oz copper) Strip Inductance = 28.8nH At 10MHz Z L = 1.86 a 3.6% error in a 50 system All dimensions are in mm Minimize Inductance 1) Use Ground plane 2) Keep length short (halving the length reduces inductance by 44%) 3) Doubling width only reduces inductance by 11%
- 15. Via Parasitics L = inductance of the via, nH H = length of via, cm D = diameter of via, cm Given: H= 0.157 cm thick board, D= 0.041 cm Via Inductance Via Capacitance L ~ 1.2nh D 2 = diameter of clearance hole in the ground plane, cm D 1 = diameter of pad surrounding via, cm T = thickness of printed circuit board, cm = relative electric permeability of circuit board material C = parasitic via capacitance, pF Given: T = 0.157cm, D 1 =0.071cm D 2 = 0.127 nH C ~ 0.51pf pF
- 16. Via Cross Section T&H D D 2 D 1
- 17. Capacitor Parasitic Model C = Capacitor R P = insulation resistance R S = equivalent series resistance (ESR) L = series inductance of the leads and plates R DA = dielectric absorption C DA = dielectric absorption
- 18. Resistor Parasitic Model R = Resistor C P = Parallel capacitance L= equivalent series inductance (ESL)
- 19. Low Frequency Op Amp Schematic
- 20. High Speed Op Amp Schematic
- 21. High Speed Op Amp Schematic Parasitic Capacitance
- 22. Stray Capacitance Simulation Schematic
- 23. Frequency Response with 2pF Stray Capacitance 1.8dB peaking 1.8dB peaking
- 24. Stray Inductance Parasitic Inductance
- 25. Parasitic Inductance Simulation Schematic AD8055 24.5mm x .25mm” =29nH
- 26. Pulse Response With and Without Ground Plane 0.6dB overshoot
- 27. Transient Response AD8009 1GHz Current Feedback Amplifier R F 150Ω 402 Ω 402 Ω R G -5V +5V 10uF 0.1uF 0.1uF 10uF
- 28. Small Changes Can Make a Big Difference! Circuit B Circuit A
- 29. Improper Use of Scope Probe Ground Clip
- 30. Effect of Clip Lead Inductance
- 31. Proper Grounding for Scope Probe in High-Speed Measurments
- 32. Small Changes Make Big Differences Circuit B Circuit A 21ns 17ns 25% reduction in ringing duration and amplitude
- 34. Ground Plane Conductor I I Dielectric Ground Plane
- 35. Sensitive Analog Circuitry Disrupted by Digital Supply Noise Ground Plane and Trace Routing Wrong Way ANALOG CIRCUITS DIGITAL CIRCUITS V D V A + + I D I A I D I A + I D V IN GND REF INCORRECT Input Connector
- 36. Sensitive Analog Circuitry Disrupted by Digital Supply Noise Ground Plane and Trace Routing Wrong Way ANALOG CIRCUITS DIGITAL CIRCUITS V D V A + + I D I A I D I A + I D V IN GND REF INCORRECT
- 37. Sensitive Analog Circuitry Safe from Digital Supply Noise Ground Plane and Trace Routing Right Way ANALOG CIRCUITS DIGITAL CIRCUITS V D V A + + V IN I D I A I D I A GND REF CORRECT
- 40. Grounding Mixed Signal ICs: Single PC Board ANALOG CIRCUITS DIGITAL CIRCUITS A A D D D V A V D ANALOG GROUND PLANE DIGITAL GROUND PLANE AGND DGND MIXED SIGNAL DEVICE A DIGITAL SUPPLY ANALOG SUPPLY SYSTEM STAR GROUND V A V D
Editor's Notes
- Welcome to the training module on Analog Devices High Speed Amplifiers Part 2 . This training module introduces the effect of PCB layout for high speed performance.
- Bypassing is essential to high speed circuit performance. Capacitors right at power supply pins provide low AC impedance to ground and local charge storage for fast rising/falling edges.
- Keep traces short to minimize inductance, trace inductance and bypass capacitor can form tank circuit and cause resonances. The resonant frequency can be determined using the equation shown here. A 1 µ H trace inductance along with a 0.1 µ f series cap will resonant at 500KHz. A small series resistor can be used to dampen the Q of the circuit and prevent the oscillation. Be careful because too large a resistor value will have large voltage drop across it.
- Keeping the load and bypass capacitors ground return close together will improve performance and can lower distortion. As this helps reduce the length the return current has to flow from the amplifier to the load and minimizes any interference with other currents circulating in the ground plane.
- Use multiple bypass capacitors and values in parallel to keep impedance down across a wide range of frequencies. A good place to start is with a 0.1 or 0.01 µF capacitor for the high frequencies and a large electrolytic for the lower frequencies a 2.2 to 10 µ F usually does the trick. Values are usually determined empirically and will be set by circuit requirements. You can see here that the combination of 2.2uF , 0.1uF and 0.01uF provides a good low impedance of 0.1 ohm from 1MHs to about 40MHz. Its important to provide a low impedance as this is the way we prevent any undesirable noise from entering the system. SMT ferrite beads are another very effective way of reducing high frequency noise from entering the board and have virtually no DC drop
- The American Heritage Dictionary defines parasites as follows An organism that grows, feeds, and is sheltered on or in a different organism while contributing nothing to the survival of its host. We can think of these parasites as little Gremlins that quite literally creep our circuits wreak havoc on your circuit. The rob performance for the circuit and contribute nothing!
- Parasitic capacitors are formed between component mounting pads and ground planes. Parasitic inductance can be formed in long traces. Parasitic resistance can be formed in ground planes. Here shows some parasitic elements in a PCB.
- Here illustrates how a parasitic capacitor can be formed and also the equation used to calculate the value of the capacitor. Removing all ground and power planes underneath any op amp input pins is recommended. This reduces the parasitic capacitance on all the pads, which is especially important as the summing node of the amplifier –IN. Remember that parasitic capacitor on –IN reduces phase margin and stability!
- Here shows an example of a parasitic pad capacitnace for an SOIC pad.
- There are a few ways to reduce parasitic capacitance, such as i ncreasing board thickness or layers, reducing trace/pad area, and removing ground plane.
- A ground plane minimizes parasitic inductance. It provides a return for the current and the passing magnetic fields cancel and thereby reduce inductance. Making a short trace is more important than making a wide trace.
- Here is an example of an of parasitic trace inductance.
- There are a few ways to reduce trace inductance, including using ground plane, keeping length short, and doubling width.
- Even if vias can introduce parasitics into a circuit, it doesn’t take many vias to start to accumulating parasitics. Multiple vias can help lower inductance, but they will increase the capacitance. It’s a trade off and each design has to consider which option is best for their application.
- This is a cross section of a via that shows the dimensions of the features from the previous slide
- When you buy a resistor or capacitor you are getting more than just a capacitor or resistor, you’re getting the parasitcs that come along with them. The complete Capacitor model has Resistances Rs and Rp. Rs is the ESR of the capacitor and it is the combined equivalent of Rs and Rp this is the AC resistance of the capacitor. Rp is the insulation resistance of the capacitor, it is a measure of the amount of dc current that flows through the dielectric of a capacitor with a voltage applied. Rp is typically 100,000M ohms or more. And RDA and CDA represent the capacitors dielectric absorption. The L represents the capacitor’s series inductance, this is big for leaded devices, but fairly small for SMT components
- Here is the complete parasitic model for a resistor. Notice that it has a lots of the same types of parasitics as the capacitor.
- Here shows a simple low frequency schematic of an amplifier in a non-inverting configuration.
- If we take into account all the high speed parasitcs for each component, the simple schematic is no longer so simple. There are all kinds of new elements introduced to the schematic, this is sometimes referred to as the “hidden schematic”. If we don’t address the parasitics it can derail the entire design. In high speed amplifiers capacitance on the input and the output can cause stability issues.
- Here shows the effects of a few pico fards of parasitic capacitance one the summing node of an amplifier.
- You can download free SPICE tool from National Instruments to simulate the effects of parasitic capacitance at the –IN of an amplifier. Here is a schematic using the AD8055 amplifier, set it for a gain of +2 and have place 2pF of capactiance on the left hand schematic and no capacitnace on the right hand schematic that is out control circuit. Let’s take a look at the effects of 2pf of stray capacitance on the inverting input. As shown, in the parasitics section 2pf is very easy to generate, just a few vias can produce 1pf quite easily.
- You can see here if we run a bode plot of the circuit we get almost 2dB of peaking from that single 2pF of capacitance.
- Nest few pages will introduces the effects of parasitic trace inductance.
- This example has placed the equivalent of 1” inch or 2.54cm of trace inductance for a value of 29nH.
- Here gets a sustained ringing throughout the duration of the pusle, not a good thing. But it does not take much to ruin circuit performance.
- Here introduces what a small change in a circuit layout can do to circuit performance. The AD8009 is used, which has a BW of 1GHz very high speed.
- Here shows two different evaluation boards, which have slightly different feedback paths. The board on the left Circuit A feedback path is longer than that of the Circuit B. It’s a small difference, but lets take a look at what the performance looks like.
- Here is the wrong way when making high speed measurments, using the long ground clip lead. This represents a lot of inductance and can create ringing and overshoot.
- This is a transient response with the clip lead not too good, notice the raggedness of pulse and all the ringing.
- This method here shows the right way to make the measurement, get rid of the probe outter plastic shield and ground clip. And make the ground contact right on the probe ground, shown here with the oval in red. No inductance, or very little and we get a nice clean pulse response.
- Here are the results of circuit A and circuit B using the proper method for picking up the scope probe ground. You can see there is a 25% reduction in overshoot and ringing.
- Ground and power planes can provide a common reference point, shielding, lower noise, lower resistance, lower impedance, reducing parasitics, heat sink, and power distribution.
- Ground plane helps reduce inductance by canceling the magnetic field. Inductance is defined as the energy stored in the field set up by the current that travels in a wire.
- Here is an example of the wrong way to set up a analog/digital or “mixed signal” PCB. This method has analog and digital sharing a common ground which will lead to noise in the ground and produce errors in the circuit. In the schematic, the current flowing in the ground inductance will generate noise voltages.
- Here is the currents going back and forth between the two digital chips will severely corrupt the analog signal. This is a wrong way!
- Here is the right way to do it. Notice the analog and digital sections are isolated and the digital current flow back and froth between the digital parts and the analog circuitry is by itself.
- Here is a grounding example. The top layer is solid ground. The bottom layer has a trace/transmission line connecting the RF connector to the load. Return current flows in the top layer ground plane directly above the trace on the opposite side.
- Here is another grounding example.
- Here shows an optimal layout for analog and digital circuits. Notice there is one and only one connection for the grounds. This is a star ground, which minimizes the interaction between analog and digital currents. Also note that the analog power supply is return to the analog ground, and the digital supply is returned to the digital ground. When using a mixed signal device make sure the grounds for it are tied to the correct grounds as shown.
- Here lists the recommendations for ground plane.
- Thank you for taking the time to view this presentation on “ High Speed Amplifiers Part 2 ” . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the Analog Devices site – link shown – or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.