R. Saravanakumar is seeking a challenging position to enhance his technical skills. He has over 5 years of experience in FPGA design and verification using Verilog, VHDL and tools like ModelSim and Xilinx ISE. Some of his projects include designing an AHB compatible DDR SDRAM controller IP core, an ATLAS processor core, and implementing Ethernet and SRAM standards on Xilinx FPGAs. He holds a BE in ECE and has experience working with organizations like Wiztech Automation Solutions and Crisp System India.

1. R.SARAVANAKUMAR
CAREER OBJECTIVE
Looking for a challenging position in an organization where I can enhance my technical skills
to the maximum extent for the symbiotic growth of the organization.
TECHNICAL SKILLS
Languages Verilog, VHDL, SystemVerilog, C
Simulation Tools ModelSim, QuestaSim, Active HDL
Synthesis Tools Xilinx ISE, Altera Quartus II, Libero IDE, Libero SOC, Synplify Pro
FPGAs Xilinx – (Spartan 3, Spartan 3E, Spartan 6, Virtex 5 ),
Altera – ( Cyclone 3, Cyclone 4 )
OS Windows, Linux (Knowledge)
AREA OF WORKING SKILLS
Standards UART, USART, JTAG, SPI, I2C, PCI, PCI Express, USB, Ethernet
SOC Standards AHB, AXI
Memories RAM, ROM, EEPROM, SRAM, DDR SDRAM
ACADEMIC QUALIFICATIONS
Degree Institution / College Board /
University
Year of
Passing
Percentage
%
BE-ECE Nandha Engineering College Anna Univertsity 2011 82
HSC Govt.Boys.Hr.Sec.School State Board 2007 86
SSLC Govt.Boys.Hr.Sec.School State Board 2005 82
102,W-Block,
2nd Avenue,2nd Floor,
Anna Nagar Rountana,
Chennai-600 040.
E-mail : saravanan.raja89@gmail.com
Mobile : + 91 7502207566
Passport : M2744166

2. PROFESSIONAL EXPERIENCES:
Organization Wiztech Automation Solutions Pvt Ltd
Designation FPGA Design & Verification Engineer
Working From July 2013 to Still date
Experience 1 Year 4 Months
Organization Crisp System India Pvt Ltd
Designation RTL Design Engineer
Worked From July 2011 to June 2013
Experience 1 Year 11 Months
RESPONSIBILITIES
• Expertise in Designing Digital Logic System using RTL HDL Coding likes, Verilog and VHDL.
• Efficient Utilization of IP Cores and FPGA features to implement Front End level logic Design.
• Simulation, Debug and Verification of Digital Logic design using Modelsim, Active-HDL,
ChipScope Pro Analyzer.
• Synthesis, Bit file generation and Targeting design to FPGA using industry standard tools and Hardware
• Capable of using industry standard EDA tools for the front-end design, Implementation and Debuggig.
• From Specification to Implementation.
PROJECTS TAKEN
 AHB Compatible DDR SDRAM Controller IP Core for ARM Based SOC
Duration Sep’2014 to Still Date
Client Wiztech Automation Solutions Pvt Ltd
Tools Modelsim, Xilinx ISE Design Tools
Languages Verilog / VHDL
FPGAs Xilnx’s FPGAs
Standards AHB, DDR SDRAM, FSM
Responsibilities
Overall Architecture Design, Written HDL Code, TestBench and
TestCases Creation, Protocol Design, Timing Path Analyze,
Implementation, On Chip Debugging
 ATLAS PROCESSOR CORE
Duration Feb’2014 to Jul’2014
Client Wiztech Automation Solutions Pvt Ltd
Tools Modelsim, Xilinx ISE Design Tools, Altera Quartus

3. Languages VHDL
FPGAs Xilinx Spartan XC3S400A, Altera Cyclone IV EP4CE22F17C6N
Standards UART, SPI EEPROM, Wishbone Bus Adaptor, Peripheral Devices
Responsibilities
Overall Architecture Design, Written HDL Code, TestBench and
TestCases Creation, Protocol Design, Timing Path Analyze,
Implementation, On Chip Debugging
 1000 BASE-X IEEE 802.3-2008 Clause 36 –Physical Coding Sublayer (PCS)
Duration Aug’2013 to Dec’2013
Client Wiztech Automation Solutions Pvt Ltd
Tools ModelSim, Xilinx ISE Design Suite
Languages Verilog
FPGAs Virtex – 5, Spartan – 6, Spatan 3E
Standards Ethernet 1000BASE-X
Responsibilities
HDL Design, TestBench Verification, Synthesis, Report Analyze,
Implementation, On Chip Debugging
 TLC
Duration Nov’2012 to Apr’2013
Client Crisp System India Pvt Ltd
Tools Modelsim, Xilinx ISE Design Tools
Language VHDL
FPGAs Spartan 3E – XC3S500E-5-PQ208
Standards UART, SPI, I2C, Chipscope Analyzer
Responsibilities Architectural Design, HDL Coding, Debugging, Implementation
 MLD:
Duration Feb’2012 to Jul ’2012
Client Crisp System India Pvt Ltd
Tools Modelsim, Xilinx ISE Design Tools
Language Verilog
FPGAs Spartan 3E – XC3S520E-4-PQ208
Standards SRAM, IP Core
Responsibilities Architectural Design, , HDL Coding, Debugging, Implementation
PERSONAL DETAILS:
Father’s Name M.Raja
Date of Birth 13.05.1989
Sex Male
Marital Status Single

4. Nationality Indian
Languages Known Tamil, English
Place Signature
Date R.SARAVANAKUMAR