This document is a resume for Shravani Nerella summarizing her education and experience. She is currently an intern at Intel working in hardware design and validation. Previously she interned at Intel in graphics validation and worked at Infosys Technologies as a software developer. She has a Master's degree in Electrical and Computer Engineering from Portland State University and is interested in opportunities in hardware design and validation.

1. SHRAVANI NERELLA shravani@pdx.edu
14827 SW Millikan Way, Beaverton, OR 97006 919-916-0303
PROFILE WWW.LINKEDIN.COM/PUB/SHRAVANI-NERELLA/49/B81/148/
 Interested in full time opportunities in hardware design and validation.
 Currently working as System Validation Engineering Intern at Intel,Hillsboro,Oregon,USA.
 Worked as Graduate Technical Intern in Graphics validation team at Intel,Folsom,CA,USA.
 Application software developer for 2 years at Infosys Technologies, India.
 Comprehensive knowledge in Integrated circuit design, Microprocessor system Design, ASIC
Design and Verilog. Strong working Knowledge on Pre/Post Si validation.
EXPERIENCE
Graduate Technical Intern in Graphics Validation team at Intel, Folsom, CA, USA – Oct’14 – Dec’14
Responsibilities:
 Developed and enabled testing of new RTL designs for HDCP encryption protocols.
 Validated upcoming ultra-HD 5K video standards using Ruby scripting and RTL emulation.
 Created a binary file parsing tool in Perl to analyze Wigig audio packet structure and contents.
 Professionally documented project requirements and best-known-methods for the team wiki page.
Systems Engineer at Infosys Technologies, India - Jun’11-Aug’13
Responsibilities and Awards:
 Providing analysis, development and design in Banking domain software using Mainframes
 Impact analysis, coding and validation of features to be integrated into existing production code.
 Awarded star performer for the year 2012-‘13.
EDUCATION
M.S., Electrical & Computer Engineering Current GPA: 4.0/4.0
Portland State University June-2015 (Expected)
Bachelor of Technology, Telecommunications GPA: 83/100 (University 8th
Rank)
Visvesvaraya Technological University, India May 2011
Relevant Courses: Digital Integrated Circuits I&II, Microprocessor System Design, Computer
Architecture, ASIC modeling and synthesis, Low Power Digital IC Design and Post Silicon Electrical
Validation. System on a Chip Design with Programmable Logic (spring’15) & Pre Silicon Validation
(spring’15).
SKILLS
Programming Languages: C++, Perl
Hardware Development Language: Verilog, VHDL
EDA Tools: Cadence, ModelSim, Xilinx ISE
Version Control: Git, Tortoise SVN
Operating Systems Environments: Windows, UNIX

2. ACADEMIC PROJECTS JAN’14-PRESENT
64 input NOR gate: Designed 64-input NOR gate for high performance and low power applications using
five different logic families viz. domino, CMOS, DCVSL, pseudo-NMOS and pass transistor.
Sizing and Stability of a SRAM cell: Analyzed read, hold and write static noise margins (SNM) of a 6T
SRAM cell. Used butterfly curve method to obtain SNM. Optimal Vmin for reliable SRAM cell is achieved.
IC Design: Design and implementation of several latches and D Flip-Flop. Analyzed back driving and
noise on both input and output end. Schematic and design of 4 x 4 Register File array with domino bitlines.
Optimized 8T cell sizes for best read and write delays. Achieved good slope on complementary bitlines.
Memory Management Unit – Verilog Simulation: Design, implementation, simulation and validation of
4-way set associative PLRU L1 Cache, TLB Cache, and page table walking and memory module. Fully
interlocked handshaking between different modules.
Processor pipeline simulation: Worked on designing, implementing a 5-stage pipeline for MIPS ISA. Stall
penalties are analyzed with and without forwarding for data hazards along with always not-taken branch
predictor.
HW Co-simulation – Memory interface: Used Nexys4 FPGA development kit for implementing hardware
co-simulation methodology with memory module on FPGA and processor module in software simulation.
Ticket Vending Machine – Verilog Simulation: Developed a ticket vending machine that accepts units of
currency as input, dispenses tickets when the required amount is deposited and tenders change.
Various VHDL models: Designed and implemented code and test benches for a FIFO controller and a
RPN calculator in VHDL. More VHDL designs including counter, two-out of five code error detector
(TOFED), data delay circuit.
REFERENCES
Available on request.