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Compiling Heterogeneous Models:
  Motivations and Challenges
Matteo Bordin, Tonu Naks, Marc Pantel and Andres Toom

          ERTS2 2012 – February 1st-3rd, Toulouse
The topic of this presentation




                                 2
Original scope of the project (2010)
• Evolve/Productize GeneAuto technology
   – A model compiler for Simulink, Stateflow and Scicos

   – ITEA project, 2005-2008 (see ERTS 2008/2010)

   – Mostly developed by IB Krates, IRIT and Alyotech

   – Validated in 2009-2010 by Airbus and Astrium (see ERTS 2010)

• Emphasis on qualification in a DO-178 context

• Small, focused project




                                                                    3
Fast  forward  to  October  2011…




                                    4
avioncis     Industrial users

                   automotive         space




Tech providers                      Academia




                                               5
Model-based integration
Qualifiable code generators
 Tunable & Open-Source
Positioning the P toolset

Specification
                                      •Conformity
   Model                              •Verifiability
                                      •Accuracy & Consistency
                                      •Compatibility
                Design
                Model
                                      •   Compliance
                                      •   Traceability
                                      •   Accuracy
                                      •   Consistency           • Compliance
                         Src Code
                                                                • Robustness




                                    Executable

                                                                         7
Or,  in  simpler  terms…


…  the  model  compiler  for



                               8
Technical approach




                     9
System Engineer                         Software Engineer                Automation Engineer
System and platform                    Architecture                         Control algorithms
                                                                            Signal processing
                                                                          Simulink®
                                       Behaviour                          Stateflow®


   subset                                  subset                             subset


     importer                                importer                          importer



                Links between
                    models
                                            Formalism




                        Integration                            Code
                        verification                         Generation




                                              Ada                C            VHDL
                                                                                                 10
Project P genealogy




                      11
SPaCIFY




          12
Ultimate goals: a tool provider perspective

• To put an end to segregation
   – Between system, software, control engineers

• To deploy a lean/agile qualification process
   – Qualify as you develop, easy re-qualification

• To build an economically viable ecosystem
   – For both tech providers and service companies




                                                     13
Ultimate goals: a scientist perspective
• To put an end to segregation between
   – System, software and control engineers

   – Industrial and academic partners

   – Formal methods and engineering tools

• To define a common intermediate language
   – Providing a well defined semantics

   – To connect analysis, synthesis and verification tools based on
     different elementary formal languages

   – To compare, improve and combine these tools

   – To connect with industrial modeling tools
                                                                      14
The challenges




                 15
Semantic convergence of DSLs (I)
• P formalism is not the union of all input languages

• Example: functional behavior
   – Synchronous state machines: Simulink, Stateflow

   – Asynchronous state machines: UML, AADL-BA

   – Execution protocols: AADL, UML

• Example: architectural modeling
   – SysML/UML/MARTE

   – AADL/ARINC-653

   – Autosar/East-ADL2 (TIMMO)

                                                        16
Example: semantic convergence of behavioral DSLs




                     Formalism




                                                   17
Semantic convergence: Current proposal
• Derived mainly from TOPCASED-AADL and GeneAuto

• Strong separation between
   – Function (derived from Synchronous MoC)
        Black box: no interaction with architecture during execution

        Synchronous w.r.t. Architecture

        Can be internally concurrent

   – Architecture (derived from AADL MoC)
        Clock management

        Synchronous/Asynchronous communication

        Distribution/Process/Thread management


                                                                       18
Verification of model-based integration
• Well beyond typing
   – Clock constraints

   – Synchronization

   – Hard real time properties

• Allocation of behavior
   – Extra functional properties are assumed to hold in simulation

   – Are they respected by the architecture?

• Support for the synthesis of software architecture
   – Logical and physical

                                                                     19
Flexible & Open Qualification
• Support for future input DSLs
   – Separable qualification evidence for:
         Importers

         Code generators

• Support for new code generation strategies
   – Separable qualification evidence for:
         Target independent model transformations

         “Printing phase”

• Toolkit shipping with qualification infrastructure
   – To allow incremental re-qualification

                                                       20
Current state at T0+4




                        21
Figuring out the consortium agreement




                                        22
Synchronizing with on-going projects
 •   CHESS, VERDE
      – Inspiration for component model and architecture modeling

 •   MBAT
      – Model verification of the P formalism

 • OPENCOSS & Safecer
      – Tooling for qualification artifact management

 •   TASTE
      – AADL tooling

 •   openETCS

 •   CESAR

 •   OPEES/PolarSys

 •   ...
                                                                    23
Technical work
• Migrating GeneAuto technology
   – Due to unclear DO-178 qualifiability of technology

• DO-178C –compliant qualification data
   – Migrating GeneAuto data

   – User-TOR, Developer-TOR,  …

• Experimenting the Open-DO collaborative platform
   – Interactive wiki instead of emails

   – Wiki pages instead of Word for deliverables



                                                          24
25

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Compiling Heterogeneous Models for Safety-Critical Systems

  • 1. Compiling Heterogeneous Models: Motivations and Challenges Matteo Bordin, Tonu Naks, Marc Pantel and Andres Toom ERTS2 2012 – February 1st-3rd, Toulouse
  • 2. The topic of this presentation 2
  • 3. Original scope of the project (2010) • Evolve/Productize GeneAuto technology – A model compiler for Simulink, Stateflow and Scicos – ITEA project, 2005-2008 (see ERTS 2008/2010) – Mostly developed by IB Krates, IRIT and Alyotech – Validated in 2009-2010 by Airbus and Astrium (see ERTS 2010) • Emphasis on qualification in a DO-178 context • Small, focused project 3
  • 4. Fast  forward  to  October  2011… 4
  • 5. avioncis Industrial users automotive space Tech providers Academia 5
  • 6. Model-based integration Qualifiable code generators Tunable & Open-Source
  • 7. Positioning the P toolset Specification •Conformity Model •Verifiability •Accuracy & Consistency •Compatibility Design Model • Compliance • Traceability • Accuracy • Consistency • Compliance Src Code • Robustness Executable 7
  • 8. Or,  in  simpler  terms… …  the  model  compiler  for 8
  • 10. System Engineer Software Engineer Automation Engineer System and platform Architecture Control algorithms Signal processing Simulink® Behaviour Stateflow® subset subset subset importer importer importer Links between models Formalism Integration Code verification Generation Ada C VHDL 10
  • 12. SPaCIFY 12
  • 13. Ultimate goals: a tool provider perspective • To put an end to segregation – Between system, software, control engineers • To deploy a lean/agile qualification process – Qualify as you develop, easy re-qualification • To build an economically viable ecosystem – For both tech providers and service companies 13
  • 14. Ultimate goals: a scientist perspective • To put an end to segregation between – System, software and control engineers – Industrial and academic partners – Formal methods and engineering tools • To define a common intermediate language – Providing a well defined semantics – To connect analysis, synthesis and verification tools based on different elementary formal languages – To compare, improve and combine these tools – To connect with industrial modeling tools 14
  • 16. Semantic convergence of DSLs (I) • P formalism is not the union of all input languages • Example: functional behavior – Synchronous state machines: Simulink, Stateflow – Asynchronous state machines: UML, AADL-BA – Execution protocols: AADL, UML • Example: architectural modeling – SysML/UML/MARTE – AADL/ARINC-653 – Autosar/East-ADL2 (TIMMO) 16
  • 17. Example: semantic convergence of behavioral DSLs Formalism 17
  • 18. Semantic convergence: Current proposal • Derived mainly from TOPCASED-AADL and GeneAuto • Strong separation between – Function (derived from Synchronous MoC) Black box: no interaction with architecture during execution Synchronous w.r.t. Architecture Can be internally concurrent – Architecture (derived from AADL MoC) Clock management Synchronous/Asynchronous communication Distribution/Process/Thread management 18
  • 19. Verification of model-based integration • Well beyond typing – Clock constraints – Synchronization – Hard real time properties • Allocation of behavior – Extra functional properties are assumed to hold in simulation – Are they respected by the architecture? • Support for the synthesis of software architecture – Logical and physical 19
  • 20. Flexible & Open Qualification • Support for future input DSLs – Separable qualification evidence for: Importers Code generators • Support for new code generation strategies – Separable qualification evidence for: Target independent model transformations “Printing phase” • Toolkit shipping with qualification infrastructure – To allow incremental re-qualification 20
  • 21. Current state at T0+4 21
  • 22. Figuring out the consortium agreement 22
  • 23. Synchronizing with on-going projects • CHESS, VERDE – Inspiration for component model and architecture modeling • MBAT – Model verification of the P formalism • OPENCOSS & Safecer – Tooling for qualification artifact management • TASTE – AADL tooling • openETCS • CESAR • OPEES/PolarSys • ... 23
  • 24. Technical work • Migrating GeneAuto technology – Due to unclear DO-178 qualifiability of technology • DO-178C –compliant qualification data – Migrating GeneAuto data – User-TOR, Developer-TOR,  … • Experimenting the Open-DO collaborative platform – Interactive wiki instead of emails – Wiki pages instead of Word for deliverables 24
  • 25. 25