1. RAMAPRASAD.B
Phone: +91-8494989888 E-Mail ID: wryamsmail@gmail.com
+91-8123515901
Objective
Seeking a job as Asic Verification (RTL verification engineer) in a reputed company
to utilize my total knowledge and experience enlarge of company.
Currently working in a Test & Verification solutions pvt ltd (T&VS).
Professional Experience
• Total 3.4 Years of Experience VLSI/ASIC (RTL) Verification.
• Knowledge in all aspects of Specification, Verification, Documentation and
Maintenance.
• Experience in Verification of IP Blocks using systemVerilog and UVM.
Personal Skills
• Problem solving and decision making ability, adapt with changes in work environment,
good team facilitator, self improvement and knowledge upgradation.
Professional Skills & Tools
HDL/HVL Verilog, System Verilog, (Little Specman)
Methodology UVM, OVM Verification Methodologies
EDA Tools Questa Sim and Cadence
Protocols AOP-SoC, MIPI-MPHY, SPI, AMBA AXI4, MIPI DSI, CAN, PUMA
SPI
Scripting Perl (Basic), C-shell

2. Position Responsibilities
• Involved in feature list extraction and development of Testbench architecture.
• Involved in Directed & Randomized Test case writing.
• Involved in development of BFM/TB ENV.
• Involved in development of Monitors, Scoreboard and checkers.
• Involved in achieving coverage 100%.
Academics
BE, Electronics & Communication Engineering from Proudhadevaraya Institute of
Technology (V T U University, Belgaum, Karnataka), 2011.
Certified Training
• Undergone Training on VERILOG, SYSTEMVERILOG, OVM and UVM in Maven Silicon
from Oct 2011 to Mar 2012 (6 months).
Work Experience
• Total 3.4 years of experience in VLSI Asic Verification.
• Working in Test And Verification Solutions, Bangalore from OCT 2012 – till date
Professional Project Work:
1. AOP(Always on power) SoC
- LG Project.
Environment: UVM, SystemVerilog, C, Cadence
Duration: Jul 2014 – DEC2015
Role:
• Understanding the Specification
• Integrated the i2c, i2s,flexfifo uart, etc vip’s in the SoC.
• Written Directed & Randomized Test cases for single & multi level protocols.
• Written tests in C as well as UVM.

3. Description :
An AOP ( Always on Power) is a SOC that is based on Internet on Things(IoT),
Which supports multiple protocols like I2C,I2S,UART,SPI,AHB,APB for communication with
Synopsys ARC processors to the external peripherals. Multiple sensors are connected to the
SOC at its peripheral to support the functionality of IoT.
2. MIPI-MPHY with Analog + Behavoural model Verification (UVM-AMS)
- LG Project.
Environment: UVM, SystemVerilog, Cadence
Duration: Dec 2014 –MAY2015
Role:
• Understanding the Specification
• Developed environment
• Written Directed & Randomized Test cases
• Written Coverage
Description :
Serial interface technology with high bandwidth capabilities, which is particularly
developed for mobile applications to obtain low pin count combined with very good power
efficiency. Mobile devices face increasing bandwidth demands for each of its functions as
well as an increase of the number of functions integrated into the system. This requires
wide bandwidth, low-pin count (serial) and highly power-efficient (network) interfaces that
provides sufficient flexibility to be attractive for multiple applications. `
3. CAN v4.2
Environment: UVM, SystemVerilog, Cadence, Questa
Duration: AUG 2014 –NOV 2014
Role:
• Understanding the Specification
• Developed environment
• Written Directed & Randomized Test cases
• Written Coverage
Description :
CAN bus is a message-based protocol, designed specifically for automotive applications
but now also used in other areas such as aerospace, maritime, industrial automation and

4. medical equipment. The CAN protocol is an international standard defined in the ISO 11898-
The improved CAN data link layer protocol is also known as CAN FD (flexible data-rate).
4. PACTRON_SPI
Environment: System verilog, Questa
Duration: MAR 2014 –JUN 2014
Role:
• Understanding the Specification
• Developed Master BFM, environment
• Written Directed & Randomized Test cases
• Coding for Coverage
Description :
The FPGA sits between the TI ARM processor module and 24 HBC ASIC’s on the board.
These 24 ASICs are calculating the double hash (SHA-256) for generating Bitcoins. Each
ASIC has 4 interfaces:
• 4-wire SPI Interface (SCK, SDI, SDO and SSEN)
• 3 Interrupts: INTO0 (Nonce overflow),INTO1 (Golden Nonce), INTO2 (Silver Nonce)
Please note that the SPI interface is only compatible to Motorola mode. The SPI bus
interfacing to the ASICs will work at maximum of 25 MHz.Please refer to Eldorado Datasheet
for complete details and some other miscellaneous parts as described in “PeerNova PetaOne
Specification”.
5. SPI_PUMA Verification
Environment: eRM, Specman, Cadence
Duration: OCT 2013 – FEB 2014
Role:
• Understanding the Specification.
• Understanding existing environment.
• Coded testcases to verify scenarios.
Description:
The SPIVID interface allows a CPU to control its external voltage supply, commonly
referred to as AVS(adaptive voltage scaling). The industry-standard SPI (serial peripheral

5. interface) allows for high-speed point-to-point connectivity to support the need for fast
adaptive voltage adjustment. A new VID (voltage identification) is sent to the regulator VRM
which will then be converted to a voltage.
6. AXI_4 Verification
Environment: UVM, System verilog, Cadence, Questa
Duration: MAY 2013 –SEP 2013
Role:
• Understanding the Specification
• Understanding existing environment
• Coding new testcases
Description
The AMBA AXI protocol supports high-performance, high-frequency system
designs, is suitable for high-bandwidth and low-latency designs, provides high-frequency
operation without using complex bridges meets the interface requirements of a wide range
of components, is suitable for memory controllers with high initial access latency and
backward-compatible with existing AHB and APB interfaces.
7. MIPI DSI IP Verification
Environment: UVM, Cadence
Duration: DEC 2012 – APR 2013
Role:
• Understanding the Specification & involved in feature list extraction
• Understanding existing environment
• Written Test cases
Description:
The Display Serial Interface Specification defines protocols between a host processor
and peripheral devices that adhere to MIPI Alliance specifications for mobile device
interfaces. The DSI specification builds on existing specifications by adopting pixel formats
and command set defined in [MIPI02],[MIPI03], and [MIPI01].

6. 8. ROUTER VERIFICATION (Institute Training Project)
Environment: System Verilog, Questa
Duration: SEP 2012 - OCT 2012
Role:
• Understanding the Specification & involved in feature list extraction
• Developing the environment
• Written Test cases
• Written the Coverage
Description:
The router accepts data packets on a single 8-bit port called data and routes the
packets to one of the three output channels, channel0, channel1 and channel2. Architected
the design and described the functionality using Verilog HDL. Architected the class based
verification environment using system Verilog Verified the RTL model using System Verilog.
Generated functional and code coverage for the RTL verification.

7. Personal details
Name : Ramaprasad B
Fathers Name : Viswanath B
Gender : Male
Marital Status : Single
Nationality : Indian
Date of Birth : 22.07.1986
Hobbies : Playing cricket, Listening to music
Languages Known : English, Kannada, Telugu and Hindi
Passport No : K8026410
Address : #1, chikkanna layout,
Maheshwari nagar, Mahadevpur,
Bangalore- 560048
Declaration:
I hereby declare that all the information furnished above is true to the best of my
knowledge and belief.
Place: Bangalore
Date:
(Ramaprasad(Ramaprasad))