1. Curriculum Vitae Abdul Naeem
Page 1 / 2
PERSONAL INFORMATION Abdul Naeem
Grytstigen 28, 1004, 14752 Tumba, Stockholm
+46-72-878-2868
abdulnaeem76@gmail.com
abduln76 (skype)
Gender Male Country Sweden (Permanent Resident)
CURRENT STATUS
R&D EXPERIENCE
OTHER EXPERIENCE
PROFESSIONAL PROJECTS
Development skills ▪ C/C++, Verilog, VHDL, SystemC, SystemVerilog, UVM, TLM, Python, FPGAProgramming, Assembly,
OpenMP, Matlab, Simulink, LabView, Embedded C-MicroC/OS-II, Agile scrum framework
EDAtools ▪ Modelsim, QuestaSim, NCSim, Synopsis DC, SoC Encounter, Quartus II, SOPC builder, Nios II IDE,
Debug Client, Xillinx ISE, GTKWave, KEIL, Pinacle, Proteus, OrCad, Altium designer, PCB creator,
Nostrum NoC, simplescalar, simics
Hardware skills
Computer skills
▪ Altera DE2-115 FPGA, Xillinx Spartan-3 FPGA, MTS-51, MTS-86C, Motorola 68000, ATmega328,
DSP, PIC 16f877a, Arduino, Raspberry-Pi
▪ Linux, Ubuntu, Fedora, Windows, Visio, Latex, Origin8, Microsoft Office and other common tools
1 Aug. 2016 – Present Hardware/Software Developer
Real Speed AB, Lund, Sweden
▪ Development of hierarchical testbenches using SystemVerilog and UVM / OVM Methodologies
▪ ASIC / SoC Design, ABV, ASIC Top Level Verification, Formal Hardware Verification
Sept. 2008 – March 2013 Researcher: Memory Models in Network-on-Chip based systems
Royal Institute of Technology (KTH), Stockholm, Sweden
▪ Realization and scalability analysis of memory models in NoC based systems
▪ Synthetic & application workloads developed. Contributed to projects (MOSART, NOSTRUM)
▪ Tools & Technologies: Verilog, VHDL, C, Assembly, SystemC, NoC tools, scripting languages
Jan. 2002 - July 2005 Assistant Manager: Electronics & embedded systems
NESCOM, Islamabad, Pakistan
▪ Designed, tested and implemented microcontrollers based circuits.
▪ Embedded software were developed and debugged both in C and assembly languages
▪ Emulation of Electronic systems. Procurement of the ICs and components
▪ Tools & Technologies: MS Visio, OrCad, PCAD, KEIL and pinnacle IDEs
Dec. 2012 - March 2016 Assistant Professor (Department of Electrical Engineering, COMSATS Institute of IT, Wah, Pakistan)
▪ R&D, teaching, supervision, counselling, administration
June 2007 - Aug. 2008
July 2005 - June 2007
Assistant Professor (Department of Electrical Engineering, COMSATS,Abbottabad, Pakistan)
▪ R&D, teaching, supervision, counselling, administration
Corrosion Engineer ( Sui Northern Gas Pipeline Limited (SNGPL), Islamabad, Pakistan)
▪ CP operations, administration, surveys, technical, record keeping
System Verilog, UVM, git,
linux, QuestaSim, scripting tools
(Aug.2016-Present)
ASIC Verification
Developed hierarchical and flexible testbenches for ethernet switch using UVM methodology. These re-
usable test benches use streaming interfaces and sequences with the main components: macros,
packages, top level module, interfaces, test modules, virtual sequences, sequence lib, sequence data,
environment_config, environment, agent_config, UVM agent, UVM_transaction, driver, monitor item,
input monitor, output monitor, UVM_subscribers, coverage and scoreboard. During this project, I have
utilized: System Verilog, UVM, git, linux, QuestaSim, and scripting tools.
2. Curriculum Vitae Abdul Naeem
EDUCATIONAND TRAINING
PERSONAL SKILLS
ADDITIONAL INFORMATION
MPSoCs
(2013-2016)
Embedded Software, FPGA
(2009)
SystemC
(2008-2016)
Shared Memory Multiprocessor Systems-on-Chip
In this project, the real time shared memory multiprocessors systems were designed and implemented
with the help of Altera’s DE2-115 FPGA development board and EDA tools (Quartus II, SOPC Builder
tool, and FPGAProgrammer, Nios II IDE and Altera debug client software).
Automatic Train Control System
In this project, Automatic Train Controller (ATC) system was designed to ensure that the trains will reach
to their destination safely without a collision. Trains between stations were emulated using DE2 board.
Bus based Processor-Memory System
In this project, bus based processor-memory systems is implemented. The two masters (source,
processor) access the memory modules (ram0, ram1) via hierarchical channel bus. Hierarchical
channel interface the masters with slaves for read/write transactions.
TLM
(2010)
System Level Design
In this project, a processor-memory system is designed that consist of three masters (M1, M2, M3) and
one slave (Memory). M1 and M2 write the data in the memory while M3 read the data from the memory
and the data is displayed on screen. The multiple masters access the memory exclusively.
ASIC, Design Compiler,
SoC encounter
(2011)
Synthesis and Physical design/ASIC
The 64 point FFT processor was designed and synthesized (using Synopsis design compiler) at
different clock period for timing analysis. The gate level simulation is performed. Physical design is done
with the help of Cadence SoC encounter tool. Floor plan, power plan, timing analysis and design
placement is done. Clock tree is inserted and synthesized. After routing, verilog netlist is simulated.
NoC Benchmarking
(2012-2013)
Parallel and Micro-Benchmark for DME/NoC Platform
Two different types of benchmarks were developed–application/ parmi benchmarks and micro-
benchmarks. These benchmarks are mapped on the NoC based multicore platform: basicmath,
bitcount, susan edge detection, susan corner detection, dijkstra, patricia, string search, and Sha.
Verilog, VHDL, C, SystemC,
Assembly, NoC, Synopsis DC
(2008-2016)
MCUs, C, Assembly, IDEs
(2013-2016, 2002-2006)
Shared Memory Coherence
NoC-based multicore platforms supporting different memory models were developed. The synthetic and
application workloads were mapped on the network to analyze the scalability of various memory
consistency models. Verilog, VHDL, C, SystemC, and NoC tools were used.
Microcontroller/Microprocessor based Design Projects
Designed various projects on different microprocessor and microcontrollers (89C51, 8085, 8086, and
68000) and developed application software both in assembly as well as in the C language. Typical
projects are: Serial Flash Programmer, SBC designed based on microcontroller, 8051 Training kit, PWM
for controlling drives voltages, programmer for serial EPROM 93C46 (I2C).
Sept. 2008 - March 2013 Ph.D (Systems-on-Chip)
▪ ICT, Royal Institute of Technology (KTH), Sweden
Aug. 2002 - May 2004 Master of Science (Electrical Engineering)
Aug. 1997 - Sept. 2001
▪ University of Engineering and Technology (UET), Taxila, Pakistan
Bachelor of Science (Electrical Engineering)
▪ University of Engineering and Technology (UET), Peshawar, Pakistan
Communication skills ▪ Fluent in English, Urdu, Pashtu (Native Language) , Swedish(B&C level)
Organisational /Managerial skills ▪ Managed research projects during PhD studies at KTH and working at CIIT
Other skills ▪ Good Team Member, Analytical Thinking, Problem Solving, Social, Keen to Learn new Technologies
Awards ▪ Awarded research grant of 0.5 Million PKR from HEC as PI
▪ Awarded scholarship for PhD Studies at KTH from HEC
Other trainings ▪ Doulos training on “Modular SystemC”, KTH, (May 2009), ACACES Summer School, Italy (2011),
UPMARC Summer School, Sweden (2009)
▪ Others: ISO/Audit(2015), NS2(2013) Corrosion(2006), Optical Fiber (2001)
