This content covers second unit COMPUTER ARCHITECTURE AND ORGANIZATION framed as per syllabus of Anna University 2017 Regulation.. This upload covers two versions of unsigned multiplication along with hardware diagram, flowchart ,example under each version

1. Computer
Architecture & organization
ALU
S.CIYAMALA KUSHBU
ASSISTANT PROFESSOR/ECE

2. MULTIPLICATION
 FIRST VERSION OR SEQUENTIAL VERSION 1.BOOTH’S ALGORITHM
 REFINED VERSION 2.BIT PAIR RECORDING OR FASTEST
MULTIPLICATION
UNSIGNED SIGNED

3. Paper and pencil based unsigned
Multiplication
RULE:
 If Multiplier is 1, Place a copy of Multipliand (i.e. 1 x Multiplicand)
 If multiplier is 0, Place 0 (i.e 0 x multiplicand)
It includes m bits * n bits = m + n bits product

4. UNSIGNED SHIFT-ADD MULTIPLICATION OR
FIRST VERSION OR SEQUENTIAL VERSION
 64 bit multiplicand reg, 64 bit ALU, 64 bit Product reg,32 bit
Multiplier reg
Hardware Diagram

5. Flowchart
ITERATION STEPS MULTIPLIER
(Mr) -3
MULTIPLICAND
(Md)-2
PRODUCT
(Prod)
0 INITIAL VALUES 0011 0000 0010 0000 0000
1 1a:LSB of Mr=1
Prod=Prod+Md
2.Shift Left Md
3.Shidt Right Mr
0011
0011
0001
0000 0010
0000 0100
0000 0100
0000 0010
0000 0010
0000 0010
2 1a:LSB of Mr=1
Prod=Prod+Md
2.Shift Left Md
3.Shidt Right Mr
0001
0001
0000
0000 0100
0000 1000
0000 1000
0000 0110
0000 0110
0000 0110
3 1a:LSB of Mr=0
No Operation
2.Shift Left Md
3.Shidt Right Mr
0000
0000
0000
0000 1000
0001 0000
0001 0000
0000 0110
0000 0110
0000 0110
4 1a:LSB of Mr=0
No Operation
2.Shift Left Md
3.Shidt Right Mr
0000
0000
0000
0001 0000
0010 0000
0010 0000
0000 0110
0000 0110
0000 0110

6. Observation on first version
½ bits in multiplicand is always zero.
Which implies 64-bit adder is wasted

7. REFINED VERSION
32 bit multiplicand reg, 32 bit ALU, 64 bit Product reg
Hardware Diagram

8. Flowchart ITERATION STEPS MULTIPLICAND
Md-4
PRODUCT
REGISTER-3
0 INTIAL VALUES 0100 0000 0011
1 1a.Prod=Prod+Md
2.Shift Right Prod
0100
0100
0100 0011
0010 0001
2 1a.Prod=Prod+Md
2.Shift Right Prod
0100
0100
0110 0001
0011 0000
3 1a.No Operation
2.Shift Right Prod
0100
0100
0011 0000
0001 1000
4 1a.No Operation
2.Shift Right Prod
0100
0100
0001 1000
0000 1100

9. Observation on Refined version
 Because product and multiplier is combined, it
has 2 steps per bit.
 Memory wastage has been removed