1. Binduhasini Sairamesh
408-963-8644 / binduhasini.sairamesh@gmail.com
Linkedin: https://www.linkedin.com/in/binduhasini-sairamesh-86834349
Education:
MS Electrical Engineering, San Jose State University, USA GPA 3.788, 2015.
ME Communication Systems, Anna University, India CGPA 9.45, 2006.
Professional work Experience:
Independent Contractor, Scalable Systems Research Labs Inc., CA, USA (Apr 2016 – Present).
 Researched the compatibility and benefits of applying CNN patent procedures in ADAS systems.
 Implemented Corner detection using a real Convolutional Neural Network in ADAS which is much simpler and
efficient and reduces the image pre-processing time by 25%.
 Developed an efficient MAC (Multiply and Accumulate) module required for the CNN core processor.
Research Intern, Volkswagen Group of America, Electronics Research Laboratory (VWoA-ERL), SJSU, CA, USA
(Feb 2015 – Jan 2016).
 Researched and developed new Computer Vision algorithms to help ADAS systems.
 Lead a team of four members, distributed the work load, organized meetups for status from each member and
synchronized the work of all the team members and presented our work during company meetups.
 Delivered complete report along with the source code in C, MATLAB, Verilog (Xilinx & Altera FPGA boards)
along with Performance Analysis comparison of speed up factor ranging from 1.79 to 341.
Teaching Experience:
Teaching Associate for ‘Digital Logic Circuits and Design’ Lab, SJSU, CA, USA (Jan 2015 – Dec 2015).
Lecturer, Vel Tech group of Engineering college, India (Jun 2006 – Oct 2006)
Assistant Professor, Narayana Engineering College, India (Aug 2002 – Mar 2004)
Project Experience in SJSU – Present:
1. Shortest path algorithm and Minimum Spanning Tree Algorithm Implementation
 Developed Djikstra’s Algorithm, Bellman-ford Algorithm, Prim and Kruskal Minimum Spanning
Tree Algorithm in C++ which passed heavy test cases of more than 40 nodes.
 Applied Quick Sort, Merge Sort, Insertion Sort, Stacks, Queues in C.
2. Real time FPGA Implementation of Illumination invariant feature point detection and tracking for
Autonomous Driver Assistance systems
 Developed a Prototype module for efficient feature point detection which are illumination invariant.
 Demonstrated the implementation of computationally intensive part of the algorithm in Altera DE1-SoC
FPGA board.
 Obtained efficient tracking of detected feature points at maximum frame rate of 80 fps and 256 MHz
performance.
3. Spread Spectrum Search Engine
 Developed a Verilog module to find a spread spectrum signal from a mixture of other signals with
noise whose architecture is similar to GPS.
 Obtained 73.33% savings of Memory due to minimal and smart coding in Verilog.
4. A Simple 8-bit Scalar Processor – Utilized VCS, Synopsys, NC-Verilog.
5. Design of Altera Nios II Instruction Subset Architecture (RISC Architecture)– Utilized Quartus-Altera tool.
6. FPGA implementation of Feature Extraction Algorithm (GFTT)
 Checked the working of a Xilinx White paper algorithm in C, MATLAB and RTL Coding and also
developed a prototype using Altera DE1 board.
 Obtained 75% similarity between FPGA and C Results through performance analysis.
7. 16-bit multiplication using only one 4-bit adder – Utilized VHDL, Modelsim, Synopsis.
Technical skills: C, MATLAB, C++, Linux, Shell scripting, Python Scripting, Verilog, VHDL, CCNA (2001)