Understanding Of PCI Express

1. Introduction
To
PCI Express

2. PCI Express
High performance I/O interconnect.
Ability to deliver low cost, high volume solution
Support multiple platform interconnect usages.

3. Advanced features
Power management
Different quality of service(QOS)
Hot-Plug & Hot-Swap support
Data Integrity
Error Handling

4. PCI Express Link
Packet
Packet

5. Link Attributes
Signaling rate
Lanes
Initialization
Symmetry

6. PCI Express Fabric Topology
CPU
Root
Complex
Memory
Switch
Legacy
Endpoint
Legacy
Endpoint
PCI Express
Endpoint
PCI Express
Endpoint
PCI Express
Endpoint
PCI Express to
PCI/PCI-X Bridge
PCI/PCI-X

7. PCI Express Layering
Transaction
Data Link
Physical
Transaction
Data Link
Physical
TX TXRX RX

8. Framing
Sequence
Number
Header Data ECRC LCRC Framing
Transaction
Data Link
Physical
Packet Flow Through the Layers

9. Transaction Layer
Assembly and Disassembly of TLPs
Flow control of TLPs
Address Spaces:
Memory
I/O
Configuration
Message

10. Services
Packet generation & processing
Generate TLPs from Device core request
Convert received packet into payload
Detect unsupported TLPs
Flow control
Support ID based ordering
Ordering rules

11. Power Management
ACPI/PCI Power Management
Hardware-controlled autonomous power management
minimizes power during full-on power state
Virtual channels & Traffic class

12. Data Link Layer
Link Management
Data Integrity
Error detection and Correction
Generate and consume DLLP

13. Services
Initialization & Power Management
Accept power state request from Transaction Layer &
convey to Physical Layer
Convey power managed state to the Transaction Layer.
Data protection
Error checking
Retry

14. Physical Layer
Includes circuitry for interface operation
Driver
Buffers
Parallel to serial conversion
Serial to parallel conversion
Exchange Information in an Implementation
specific format
Convert Information into serialized format

15. Services
Interface initialization, maintenance control
Interconnect power management
Width & Lane mapping negotiation
8b/10b Encoding/Decoding
Embedded clock tuning & alignment
Symbol & special Ordered set generation
Symbol transmission & alignment
Transmission & Reception circuits
Elastic buffer at receiving side

16. Inter-Layer Interface
Transaction/Data Link Interface
Transaction to Data Link Interface
Byte or multi byte data to be sent
Requested power state for the Link
Data Link to Transaction Interface
Byte or multi byte data received
TLP framing information for the received byte
Actual power state for the Link
Link status information

17. Inter-Layer Interface
Data Link / Physical Interface
Physical to Data Link Interface
TLP & DLLP boundary information
Requested power state for the Link
Data Link to Physical Interface
Byte or multi byte data received
TLP & DLLP framing information
Indication of errors detected by Physical Layer
Connection status information