Serial ATA (SATA) is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives and optical drives. Serial ATA replaces the older AT Attachment standard (later referred to as Parallel ATA or PATA), offering several advantages over the older interface: reduced cable size and cost (seven conductors instead of 40 or 80), native hot swapping, faster data transfer through higher signalling rates, and more efficient transfer through an (optional) I/O queuing protocol.
Serial ATA (SATA) is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives and optical drives. Serial ATA replaces the older AT Attachment standard (later referred to as Parallel ATA or PATA), offering several advantages over the older interface: reduced cable size and cost (seven conductors instead of 40 or 80), native hot swapping, faster data transfer through higher signalling rates, and more efficient transfer through an (optional) I/O queuing protocol.
Get it right the first time lpddr4 validation and compliance testBarbara Aichinger
JEDEC LPDDR4 Compliance and Validation Testing. Learn about electrical and protocol testing and validation. DDR Memory is in almost all computing devices today.
Highlighted notes while studying Concurrent Data Structures:
DDR4 SDRAM
Source: Wikipedia
Double Data Rate 4 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR4 SDRAM, is a type of synchronous dynamic random-access memory with a high bandwidth ("double data rate") interface.
Wikipedia is a free online encyclopedia, created and edited by volunteers around the world and hosted by the Wikimedia Foundation.
I2C is a serial protocol for two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in embedded systems.
USB 3.1 Gen 2 Compliance Testing and Debug Webinarteledynelecroy
Join Teledyne LeCroy for this free webinar as we analyze the major changes in the standard compared to its previous versions and offer solutions for compliance testing and debug to help in analysis and characterization of USB 3.1 Gen 2 signals and interfaces.
The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture (AMBA) protocol family. It defines a low-cost interface that is optimized for minimal power consumption and reduced interface complexity.
Get it right the first time lpddr4 validation and compliance testBarbara Aichinger
JEDEC LPDDR4 Compliance and Validation Testing. Learn about electrical and protocol testing and validation. DDR Memory is in almost all computing devices today.
Highlighted notes while studying Concurrent Data Structures:
DDR4 SDRAM
Source: Wikipedia
Double Data Rate 4 Synchronous Dynamic Random-Access Memory, officially abbreviated as DDR4 SDRAM, is a type of synchronous dynamic random-access memory with a high bandwidth ("double data rate") interface.
Wikipedia is a free online encyclopedia, created and edited by volunteers around the world and hosted by the Wikimedia Foundation.
I2C is a serial protocol for two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in embedded systems.
USB 3.1 Gen 2 Compliance Testing and Debug Webinarteledynelecroy
Join Teledyne LeCroy for this free webinar as we analyze the major changes in the standard compared to its previous versions and offer solutions for compliance testing and debug to help in analysis and characterization of USB 3.1 Gen 2 signals and interfaces.
The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture (AMBA) protocol family. It defines a low-cost interface that is optimized for minimal power consumption and reduced interface complexity.
WSN protocol 802.15.4 together with cc2420 seminars Salah Amean
WSN protocol 802.15.4 together with cc2420 seminars . It is based on the standand of ieee802.15.4 and data sheet of the radio transceiver cc2420.
Note that some slides are borrowed.
1. An Overview of Serial ATA Technology Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 [email_address]
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10. SATA Architectural Model Application Transport Link Physical Device Control Software Buffer Memory DMA management Serial digital transport control Serial digital link control Serial physical interface Device Layers Host Control Software Buffer Memory DMA management Host Layers Serial digital transport control Serial digital link control Serial physical interface
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15. Out of Band Signal Forms COMRESET / COMINIT COMWAKE 106.7 ns 106.7 ns 106.7 ns 320 ns
16. Out of Band Signaling Protocol COMRESET COMWAKE COMINIT COMWAKE Host Device
17. SATA Port Model Clock & Data Recovery Serializer Deserializer Analog Front End OOB Detect COMRESET / COMINIT COMWAKE Data Out RX Clock Port Control Logic Tx Clock Align Generator Data In Phy Reset Phy Ready Slumber Partial SPD Mode System Clock SPD Select Tx + Tx - Rx - Rx +
18. SATA Architectural Model Application Transport Link Physical Device Control Software Buffer Memory DMA management Serial digital transport control Serial digital link control Serial physical interface Device Layers Host Control Software Buffer Memory DMA management Host Layers Serial digital transport control Serial digital link control Serial physical interface
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22. CRD+ & CRD- Encoded Characters 0 0 1 1 1 1 1 1 1 0 1 0 1 1 1 0 0 1 0 1 0 1 0 0 1 0 0 1 8b Character 0x3F This 10b Character transmitted when CRD negative This 10b Character transmitted when CRD positive This character 6 ones 4 zeros Disparity +2 This character 4 ones 6 zeros Disparity -2
37. SATA Architectural Model Application Transport Link Physical Device Control Software Buffer Memory DMA management Serial digital transport control Serial digital link control Serial physical interface Device Layers Host Control Software Buffer Memory DMA management Host Layers Serial digital transport control Serial digital link control Serial physical interface
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40. FIS types D H Data 46h D H PIO Setup 5Fh D H BIST Activate 58h D H DMA Setup 41h D H DMA Activate 39h D H Set Device bits A1h D H Register transfer device to host 34h H D Register transfer host to device 27h Direction Description FIS TYPE CODE
41. Register – Host to Device FIS Reserved Reserved Reserved Reserved Dword 4 Sector Count Sector Count Reserved Control Dword 3 Sector Number Cyl Low (exp) Cyl High (exp) Features (exp) Dword 2 Sector Number Cyl Low Cyl High Dev/Head Dword 1 FIS TYPE (27h) Reserved Command Features Dword 0 Byte 0 Byte 1 Byte 2 Byte 3
42. BIST Activate FIS T - Far end transmit only – transmit Dwords defined in words 1 & 2 A - No ALIGN transmission (valid only with T) S - Bypass scrambling (valid only with T) L - Far end retimed loopback with ALIGN insertion F - Far end analog loopback P - Transmit primitives defined in words 1 & 2 of the FIS R - Reserved V - Vendor Unique Test Mode – other bits undefined Data [7:0] Data [15:8] Data [23:16] Data [31:24] 2 Data [7:0] Data [15:8] Data [23:16] Data [31:24] 1 FIS Type 58h Reserved [ TASLFPRV ] Reserved 0 Byte 0 Byte 1 Byte 2 Byte 3
43. Data FIS Dword N . . . Dword 2 N Dwords of Data Minimum 1 Dword Maximum 2048 Dwords Dword 1 FIS TYPE (46h) Reserved Reserved Reserved Dword 0 Byte 0 Byte 1 Byte 2 Byte 3
44. SATA Architectural Model Application Transport Link Physical Device Control Software Buffer Memory DMA management Serial digital transport control Serial digital link control Serial physical interface Device Layers Host Control Software Buffer Memory DMA management Host Layers Serial digital transport control Serial digital link control Serial physical interface
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