Fresher Resume for semiconductor domain.

1. HEMANTH KUMAR MOTAMARRI
Contact: +91 9490137816 | Email:motamarrihemanth7@gmail.com
EDUCATION
2016 M.Tech (VLSI) JNTU Kakinada University,Kakinada 75.00%
2014 B.Tech (ECE) PSCMR college of Engg and tech,Vijayawada 74.31 %
2010 Intermediate(MPC) Sri Chaitanya Junior College, Vijayawada 94.50%
2008 SSC Chegu Vidyalayam, Jaggayyapeta 90.00%
ACHIEVEMENTS
 Secured a rank in top 13% in Gate-2014 (ECE).
 Secured 853rdrank in 10th NATIONAL IT APTITUDE TEST conducted by ORACLE (out of 80,000 applicants).
 Achieved 1st prize in Inter State Mathematics Competiton Test – 2006 and 2005 (District level).
SKILLS
 HDL & HVL : Verilog , Basics in System Verilog. Scripting : Basics in Tcl ,Perl & Python.
 Tools: Synopsys ,Xilinx. Programming: Basics in C.
PROJECTS
Built in generation of functional broad side tests using fixed hardware structure using verilog. M.Tech(Main Project)
 The main objective of this project is to test a design named S27 by generating some test patterns with less complexity.
 Here the test patterns are to be generated while design is working (FUNCTIONAL) and should be flexible to be used
for other designs (BROAD SIDE) and the h/w used to generate patterns is attached to the design (FIXED HARDWARE).
 S27 design accepts an input of 4 bit size and also contains 3 FF’s.
Role: I used 12 bit LFSR to generate test patterns, fed these to a decoder to get a 4 bit pattern and avoided synchronization.
 I tested S27 not only by test patterns from LFSR but also from system input (4 bit).MUX is used to select either.
 I compared the outputs of ideal S27 circuit and experimental S27 circuit to know the faults in experimental circuit.
 In this I compared the outputs of 3 FF’s also from both the circuits which ultimately increased the fault coverage.
 I reduced the power(clock)by using a circuit Bit swapping LFSR.It generates patterns from existing by swapping values.
Physical Design of PARSER. M.Tech(Mini Projects)
 Parser is an unknown design given by vendor.In this I performed PD flow for the design using synopsys IC compiler.
Design , simulation of USB 3.0 Super speed Physical Layer.
 The main aim of this project is to design the data flow between Transmitter and Receiver for USB 3.0 Physical Layer.
 In this project 8b data is transmitted, encoded to 10b (symbol) and was converted to serial bit stream in Tx section.
 The Rx section receives the serial data and uses this for clock recovery by DPLL.This clock is used further in Rx section.
 Serial data is converted to parallel and then stored in a buffer.Data validity is checked and then it is decoded.
Role: In this i did encoding (8b/10b) and decoding (10b/8b) of data at Tx and Rx sections respectively.
 The 8 bit data is divided in to two parts of 3b and 5b respectively where 3b/4b and 5b/6b is done called as vectors.
 Each 4b and 6b are generated such that their disparities are of +2 or 0 or -2.
 In some cases two types of vectors can be generated-primary and alternate which are complement to each other.
 Primary vector is generated first.If the running and required disparities are different then alternate vecotr is chosen.
 This disparity selection is helpful in maintaining equal no: of 1’s and 0’s throughout the transfer.
 This maintains transfer rate to either 2.5GT/s or 5.0GT/s running on 125 MHz and 250MHz clock respectively.
Design and simulation of Elevator based Control system using verilog.
 Elevator controls the operation of dual elevator system (up & down) and is implemented for multi-storage building.
 Different sensors in it sense the position of Elevator and the requests are read through FF’s.
Role: I wrote the control algorithm for 4 floor multi-storage to get the postion of elevator under reset condition.
 Reset is removed while moving and then next postion is calculated using FF’s and values are assigned.
 Next position could be from any of the floors either internally or externally.
Orthogonal space-time block codes for MIMO OFDM chanels using MATLAB. B.Tech
 A class of Space-Time Block codes over Frequency Selective Ray leigh fading channel are proposed.
 This technique is mainly used to improve the transfer rate by using Multiple Transmitting and receiving antennas.
Role : Designed data transfer b/w 2 transmitting & 2 receiving antennas where 2 antennas send 2 bits in one time instance.
 I sent 1 bit by 1 antenna(totally 2 bits) at 1st time instance & sent complex conjugate of the data at 2nd time instance.
 2 receiving antennas are present.The 1st receiving antenna receives the combination of 2 transmitters at 1st instance.
 And the 2nd receiving antenna receives the combination of data sent by 2 transmitting antennas in 2nd time instance.
CAREER OBJECTIVE
To obtain a position in a people-oriented organization where I can maximize my experience in a challenging
environment to achieve the corporate goals.