Electrical engineering

1. Chapter 3:
Sequential Logic Design
(Part 2.1)
EET107/3
DIGITAL ELECTRONICS 1

2. 3.2 COUNTER
INTRODUCTION
 A counter – a group of flip-flops connected together to
perform counting operations.
 The number of flip-flops used and the way in which they are
connected determine the number of states (modulus).
 Two broad categories according to the way they are clocked:
Asynchronous counter
Synchronous counter

3. SYNCHRONOUS COUNTER
A 2-bit synchronous binary counter:

4. SYNCHRONOUS COUNTER
Timing details for the 2-bit synchronous counter operation (the
propagation delays of both flip-flops are assumed to be equal):

5. SYNCHRONOUS COUNTER
The Binary State Sequence:
CLOCK
PULSE
Q1 Q0
Initially 0 0
1 0 1
2 1 0
3 1 1
4 (recycles) 0 0

6. SYNCHRONOUS COUNTER
A 3-bit synchronous binary counter:

7. SYNCHRONOUS COUNTER
The Binary State Sequence for a 3-bit Binary Counter:
CLOCK PULSE Q2 Q1 Q0
Initially 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 (recycles) 0 0 0

8. SYNCHRONOUS COUNTER
A 4-bit synchronous binary counter and timing diagram. Points where the AND
gate outputs are HIGH are indicated by the shaded areas.

9. SYNCHRONOUS COUNTER
A 4-Bit Synchronous BCD Decade Counter:

10. SYNCHRONOUS COUNTER
The Binary State Sequence for BCD Decade Counter:
CLOCK PULSE Q3 Q2 Q1 Q0
Initially 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 (recycles) 0 0 0 0

11. DESIGN OF SYNCHRONOUS COUNTER
General clocked sequential circuit.

12. DESIGN OF SYNCHRONOUS COUNTER
Steps used in the design of sequential circuit:
1. Specify the counter sequence and draw a state diagram
2. Derive a next-state table from the state diagram
3. Develop a transition table showing the flip-flop inputs
required for each transition. The transition table is always the
same for a given type of flip-flop
4. Transfer the J and K states from the transition table to K-
maps. There is a K-map for each input of each flip-flop.
5. Group the K-map cells to generate and derive the logic
expression for each flip-flop input.
6. Implement the expressions with combinational logic, and
combine with the flip-flops to create the counter.

13. DESIGN OF SYNCHRONOUS COUNTER
Example:
1. Design a Modulus-4 synchronous up-counter. Use D flip-flops.
2. Design a Modulus-4 synchronous up-counter. Use T flip-flops.
3. Design a Modulus-4 synchronous up-counter. Use JK flip-flops.
4. Design a Modulus-4 synchronous up-counter. Use SR flip-flops.

14. DESIGN OF SYNCHRONOUS COUNTER
Example: Design 3-bit Gray code counter by using JK, T, D and SR
flip-flop.
Step 1:
State diagram for a 3-bit Gray code counter.

15. DESIGN OF SYNCHRONOUS COUNTER
Next-state table for a 3-bit Gray code counter.
Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
0 0 1 0 1 1
0 1 1 0 1 0
0 1 0 1 1 0
1 1 0 1 1 1
1 1 1 1 0 1
1 0 1 1 0 0
1 0 0 0 0 0

16. TRANSITION TABLE FOR A J-K FLIP-FLOP
QN : present state
QN+1: next state
X: Don’t care
Output Transitions Flip-flop Inputs
QN QN+1 J K
0  0 0 X
0  1 1 X
1  0 X 1
1  1 X 0

17. KARNAUGH MAPS FOR PRESENT-STATE J AND K INPUTS.

18. THREE-BIT GRAY CODE COUNTER.

19. EXAMPLE:
DESIGN A COUNTER WITH THE IRREGULAR BINARY COUNT SEQUENCE AS
SHOWN IN THE STATE DIAGRAM. USE J-K FLIP-FLOPS

20. NEXT-STATE TABLE
Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0
0 0 1 0 1 0
0 1 0 1 0 1
1 0 1 1 1 1
1 1 1 0 0 1

21. TRANSITION TABLE FOR A J-K FLIP-FLOP
Output Transitions Flip-flop Inputs
QN QN+1 J K
0  0 0 X
0  1 1 X
1  0 X 1
1  1 X 0

22. K-MAP

23. THE COUNTER CIRCUIT

24. EXAMPLE :
STATE DIAGRAM FOR A 3-BIT UP/DOWN GRAY CODE COUNTER.

25. THE 74HC163 4-BIT SYNCHRONOUS BINARY COUNTER. (THE QUALIFYING
LABEL CTR DIV 16 INDICATES A COUNTER WITH SIXTEEN STATES.)

26. TIMING EXAMPLE FOR A 74HC163.

27. THE 74LS160 SYNCHRONOUS BCD DECADE COUNTER. (THE QUALIFYING
LABEL CTR DIV 10 INDICATES A COUNTER WITH TEN STATES.)

28. TIMING EXAMPLE FOR A 74LS160.

29. UP/DOWN SYNCHRONOUS COUNTER
A BASIC 3-BIT UP/DOWN SYNCHRONOUS COUNTER.

30. TIMING DIAGRAM

31. THE 74HC190 UP/DOWN SYNCHRONOUS DECADE COUNTER.

32. TIMING EXAMPLE FOR A 74HC190.

33. J AND K MAPS FOR TABLE 9-11. THE UP/DOWN CONTROL INPUT, Y, IS
TREATED AS A FOURTH VARIABLE.

34. THREE-BIT UP/DOWN GRAY CODE COUNTER.

35. CASCADE COUNTERS
Two cascaded counters (all J and K inputs are HIGH).

36. A MODULUS-100 COUNTER USING TWO CASCADED DECADE COUNTERS.

37. THREE CASCADED DECADE COUNTERS FORMING A DIVIDE-BY-1000
FREQUENCY DIVIDER WITH INTERMEDIATE DIVIDE- BY-10 AND DIVIDE-BY-100
OUTPUTS.

38. EXAMPLE:
DETERMINE THE OVERALL MODULUS OF THE TWO CASCADED COUNTER FOR (A) AND (B)
For (a) the overall modulus for the 3 counter
configuration is 8 x 12 x 16 = 1536
for (b) the overall modulus for the 4 counter configuration
is 10 x 4 x 7 x 5 = 1400

39. A DIVIDE-BY-100 COUNTER USING TWO 74LS160 DECADE COUNTERS.

40. A DIVIDE-BY-40,000 COUNTER USING 74HC161 4-BIT BINARY COUNTERS.
NOTE THAT EACH OF THE PARALLEL DATA INPUTS IS SHOWN IN BINARY ORDER
(THE RIGHT-MOST BIT D0 IS THE LSB IN EACH COUNTER).

41. DECODING OF STATE 6 (110).
COUNTER DECODING
* To determine when the counter is in a certain states in its
sequence by using decoders or logic gates.

42. A 3-BIT COUNTER WITH ACTIVE-HIGH DECODING OF COUNT 2 AND COUNT 7.

43. A BASIC DECADE (BCD) COUNTER AND DECODER.

44. OUTPUTS WITH GLITCHES FROM THE PREVIOUS DECODER. GLITCH WIDTHS ARE EXAGGERATED FOR
ILLUSTRATION AND ARE USUALLY ONLY A FEW NANOSECONDS WIDE.

45. THE BASIC DECADE COUNTER AND DECODER WITH STROBING TO ELIMINATE
GLITCHES.

46. STROBED DECODER OUTPUTS FOR THE CIRCUIT

47. SIMPLIFIED LOGIC DIAGRAM FOR A 12-HOUR DIGITAL CLOCK.

48. LOGIC DIAGRAM OF TYPICAL DIVIDE-BY-60 COUNTER USING 74LS160A SYNCHRONOUS
DECADE COUNTERS. NOTE THAT THE OUTPUTS ARE IN BINARY ORDER (THE RIGHT-MOST
BIT IS THE LSB).

49. LOGIC DIAGRAM FOR HOURS COUNTER AND DECODERS. NOTE THAT ON THE
COUNTER INPUTS AND OUTPUTS, THE RIGHT-MOST BIT IS THE LSB.

50. FUNCTIONAL BLOCK DIAGRAM FOR PARKING GARAGE CONTROL.

51. LOGIC DIAGRAM FOR MODULUS-100 UP/DOWN COUNTER FOR AUTOMOBILE
PARKING CONTROL.

52. PARALLEL-TO-SERIAL DATA CONVERSION LOGIC.

53. EXAMPLE OF PARALLEL-TO-SERIAL CONVERSION TIMING FOR THE PREVIOUS CIRCUIT

54. THANK YOU