Latches, Flip-flops - SR, JK, D, T, and Master-Slave Characteristic table and equation,counters and their design, Synchronous counters – Synchronous Up/Down counters – Programmable counters – State table and state transition diagram ,sequential circuits design methodology. Registers –shift registers.

1. UNIT 5
Sequential Circuits

2. Sequential Circuits
Latches,
Flip-flops - SR, JK, D, T, and Master-Slave Characteristic table and
equation
counters and their design,
Synchronous counters – Synchronous Up/Down counters
– Programmable counters – State table and state transition diagram ,
sequential circuits design methodology.
Registers –shift registers.

3. Sequential Circuits
A sequential circuit refers to a special type of circuit.
It consists of a series of various inputs and outputs.
Here, the outputs depend on a combination of both the present
inputs as well as the previous outputs.
This previous output gets treated in the form of the present state.
But sequential circuit has memory so output can vary based on
input.
This type of circuits uses previous input, output, clock and a memory
element.

4. Sequential Circuits

5. Flip Flop
Flip flop is a sequential circuit which generally samples
its inputs and changes its outputs only at particular
instants of time and not continuously.
Flip flop is said to be edge sensitive or edge triggered
rather than being level triggered like latches.

6. S-R Flip Flop
It is basically S-R latch using NAND gates with an
additional enable input.
It is also called as level triggered SR-FF.
For this, circuit in output will take place if and only if the enable input
(E) is made active.
In short this circuit will operate as an S-R latch if E = 1 but there is no
change in the output if E = 0.
characteristics equations for flip flops: Qn+1 = S + R
̅ Qn

11. JK Flip Flop
The JK Flip-flop is similar to the SR Flip-flop but there is no change in state
when the J and K inputs are both LOW.
in sequential logic circuits but it suffers from two basic switching problems.
1. the Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided
2. if Set or Reset change state while the enable (EN) input is high the correct
latching action may not occur
Then to overcome these two fundamental design problems with the SR flip-
flop design, the JK flip Flop was developed.

15. Master-Slave JK Flip-flop
The master-slave flip-flop eliminates all the timing problems by using two
SR flip-flops connected together in a series configuration.
One flip-flop acts as the “Master” circuit, which triggers on the leading
edge of the clock pulse while the other acts as the “Slave” circuit, which
triggers on the falling edge of the clock pulse.
This results in the two sections, the master section and the slave section
being enabled during opposite half-cycles of the clock signal.

16. Master-Slave JK Flip-flop
The Master-Slave Flip-Flop is basically two gated SR flip-flops
connected together in a series configuration with the slave having an
inverted clock pulse.
The outputs from Q and Q from the “Slave” flip-flop are fed back to
the inputs of the “Master” with the outputs of the “Master” flip flop
being connected to the two inputs of the “Slave” flip flop.
This feedback configuration from the slave’s output to the master’s
input gives the characteristic toggle as shown below.

17. Master-Slave JK Flip-flop

18. Delay Flip Flop / D Flip Flop
Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND
inverter connected between S and R inputs.
It has only one input.
The input data is appearing at the output after some time.
Due to this data delay between i/p and o/p, it is called delay flip flop.
S and R will be the complements of each other due to NAND inverter.
Hence S = R = 0 or S = R = 1, these input condition will never appear. This
problem is avoid by SR = 00 and SR = 1 conditions.
Qn+1 = JQ
̅ n + K
̅ Qn

22. Toggle Flip Flop / T Flip Flop
Toggle flip flop is basically a JK flip flop with J and K
terminals permanently connected together.
It has only input denoted by T as shown in the Symbol
Diagram.
The symbol for positive edge triggered T flip flop is shown
in the Block Diagram.

26. Counters and their design
Synchronous counters
Synchronous Up/Down counters
– Programmable counters – State table and
state transition diagram ,
sequential circuits design methodology.

27. Counters and their design :
A special type of sequential circuit used to count the pulse is known as a
counter, or a collection of flip flops where the clock signal is applied is
known as counters.
The counter is one of the widest applications of the flip flop. Based on the
clock pulse, the output of the counter contains a predefined state. The
number of the pulse can be counted using the output of the counter.

29. It is a group of flip-flops with a clock signal applied.
Counters are of two types.
(1)Asynchronous or ripple counters.
(2)Synchronous counters.

30. Asynchronous or ripple counters:
The external clock signal is applied to one flip flop and then
output of preceding flip flop is connected to the clock of next flip
flop.
Ripple counter is a special type of Asynchronous counter in which
the clock pulse ripples through the circuit.
The n-MOD ripple counter forms by combining n number of flip-
flops.
The n-MOD ripple counter can count 2n states, and then the
counter resets to its initial value.

32. The logic diagram of a 2-bit ripple up counter is shown in
figure. The toggle (T) flip-flop are being used.
But we can use the JK flip-flop also with J and K connected
permanently to logic 1.
External clock is applied to the clock input of flip-flop
A and QA output is applied to the clock input of the next flip-
flop i.e. FF-B.

39. Synchronous counters:
If the "clock" pulses are applied to all the flip-flops in a counter
simultaneously, then such a counter is called as synchronous
counter.
2-bit Synchronous up counter
The JA and KA inputs of FF-A are tied to logic 1. So FF-A will
work as a toggle flip-flop. The JB and KB inputs are connected to
QA.

46. Classification of counters
Depending on the way in which the counting progresses, the
synchronous or asynchronous counters are classified as follows
−
1.Up counters
2.Down counters
3.Up/Down counters

47. UP/DOWN Counter:
Up counter and down counter is combined together to obtain an
UP/DOWN counter.
A mode control (M) input is also provided to select either up or
down mode.
A combinational circuit is required to be designed and used
between each pair of flip-flop in order to achieve the up/down
operation.
Type of up/down counters
UP/DOWN ripple counters
UP/DOWN synchronous counter

48. UP/DOWN Ripple Counters
In the UP/DOWN ripple counter all the FFs operate in the toggle mode.
So either T flip-flops or JK flip-flops are to be used.
The LSB flip-flop receives clock directly. But the clock to every other
FF is obtained from (Q = Q bar) output of the previous FF.
UP counting mode (M=0) − The Q output of the preceding FF is
connected to the clock of the next stage if up counting is to be
achieved. For this mode, the mode select input M is at logic 0 (M=0).
DOWN counting mode (M=1) − If M = 1, then the Q bar output of the
preceding FF is connected to the next FF. This will operate the counter
in the counting mode.

51. Registers –shift
registers.

52. Register
• one flip-flop can store one-bit of information. In order to
store multiple bits of information, we require multiple
flip-flops. The group of flip-flops, which are used to
hold ,store the binary data is known as Register.
• If the register is capable of shifting bits either towards
right hand side or towards left hand side is known as Shift
register. An ‘N’ bit shift register contains ‘N’ flip-flop.

53. the four types of shift registers based on applying
inputs and accessing of outputs.
1.Serial In − Serial Out shift register
2.Serial In − Parallel Out shift register
3.Parallel In − Serial Out shift register
4.Parallel In − Parallel Out shift register

54. 1.Serial In − Serial Out shift register
(SISO Shift Register)
•The shift register, which allows serial input
and produces serial output is known as Serial
In – Serial Out SISOSISO shift register.
•The block diagram of 3-bit SISO shift register
is shown in the following figure.
•Similarly, the N-bit SISO shift
register requires 2N-1 clock pulses in order to
shift ‘N’ bit information.

56. This block diagram consists of three D flip-flops, which are cascaded.
That means, output of one D flip-flop is connected as the input of next D
flip-flop.
All these flip-flops are synchronous with each other since, the same clock
signal is applied to each one.
In this shift register, we can send the bits serially from the input of left most
D flip-flop.
Hence, this input is also called as serial input.
For every positive edge triggering of clock signal, the data shifts from one
stage to the next.
So, we can receive the bits serially from the output of right most D flip-flop.
Hence, this output is also called as serial output.

57. 2.Serial In - Parallel Out SIPO Shift Register
• The shift register, which allows serial input and
produces parallel output is known as Serial In –
Parallel Out SIPOSIPO shift register.
• The block diagram of 3-bit SIPO shift register is
shown in the following figure.
• Similarly, the N-bit SIPO shift register requires N clock
pulses in order to shift ‘N’ bit information.

59. This circuit consists of three D flip-flops, which are cascaded.
That means, output of one D flip-flop is connected as the input of next D flip-
flop.
All these flip-flops are synchronous with each other since, the same clock
signal is applied to each one.
In this shift register, we can send the bits serially from the input of left most
D flip-flop. Hence, this input is also called as serial input.
For every positive edge triggering of clock signal, the data shifts from one
stage to the next.
In this case, we can access the outputs of each D flip-flop in parallel. So, we
will get parallel outputs from this shift register.

60. 3.Parallel In − Serial Out PISO Shift Register
• The shift register, which allows parallel input and produces
serial output is known as Parallel In − Serial
Out PISOPISO shift register. The block diagram of 3-bit PISO
shift register is shown in the following figure.
• the N-bit PISO shift register requires N-1 clock pulses in
order to shift ‘N’ bit information.

62. This circuit consists of three D flip-flops, which are
cascaded.
That means, output of one D flip-flop is connected as the
input of next D flip-flop.
All these flip-flops are synchronous with each other since,
the same clock signal is applied to each one.
In this shift register, we can apply the parallel inputs to
each D flip-flop by making Preset Enable to 1.
For every positive edge triggering of clock signal, the data
shifts from one stage to the next. So, we will get the serial
output from the right most D flip-flop.

63. 4.Parallel In - Parallel Out PIPO Shift Register
• The shift register, which allows parallel input and produces parallel
output is known as Parallel In − Parallel Out PIPOPIPO shift register.
The block diagram of 3-bit PIPO shift register is shown in the
following figure.
• Similarly, the N-bit PIPO shift register doesn’t require any clock pulse
in order to shift ‘N’ bit information.