This document discusses synchronous sequential circuits and various types of flip-flops and counters. It begins with definitions of synchronous circuits and differences between latches and flip-flops. It then explains the operation of common flip-flop types including SR, D, JK, and T flip-flops. Next, it covers analysis and design of clocked sequential circuits using Moore and Mealy models. Finally, it discusses various counter types such as ripple, ring, and shift registers with examples.

1. R.M.K COLLEGE OF ENGINEERING & TECHNOLOGY
DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
EC8392- DIGITAL ELECTRONICS
UNIT-III
By
S.Sesha Vidhya /ASP/ECE

2. UNIT III
SYNCHRONOUS SEQUENTIAL CIRCUITS
Flip flops – SR, JK, T, D, Master/Slave FF – operation and excitation tables,
Triggering of FF, Analysis and design of clocked sequential circuits – Design -
Moore/Mealy models, state minimization, state assignment, circuit
implementation – Design of Counters- Ripple Counters, Ring Counters,
Shift registers, Universal Shift Register

4. Synchronous Sequential Circuits
• Synchronous circuit is a digital circuit in which the changes in the state of memory
elements are synchronized by a clock signal.
• In a sequential digital logic circuit, data is stored in memory devices called flip-flops or
latches.
• Memory element is classified into TWO types
• Latch
• Flip-flop

5. LATCHESVs FLIP FLOP

6. Memory Element

7. Level triggering and Edge triggering

8. Flip-Flop
Is a memory element used in sequential circuit that
stores one bit of information
Types of FF
1. SR FF
2. D FF
3. JK FF
4. T FF

9. SR Flip-Flop
Logic Diagram
NOR gate and NAND gate are used in the design
SR FF using NAND gate SR FF using NOR gate

10. SR FF FunctionTable and Logic Diagram
SR FF FunctionTable
Clocked SR with NAND gates

11. Clocked SR with NOR gates

12. ExcitationTable of SR FF
State Diagram

13. D Flip-Flop
Toeliminate the undesirable condition of the forbidden state in an SR FF i.e,
S and R inputs are never equal to 1 at the same time. This is done by delay
FF.
D FF using NAND gate D FF using NOR gate

14. D FF Function Table
D FF Excitation Table
D FF Characteristic Equation
D FF Characteristic Table

15. D FF State Diagram
D FF is used for data transfer between input and output. Hence this circuit is known as
transparentlatch
D FF Characteristic Table

16. JK Flip-Flop
Has two inputs i.e, J and K. J – Set input
K – Reset input
Can be obtained from the clocked SR FF by adding
two AND gates
JK FF using NAND gates
JK FF using NOR gates

17. JK FF Function Table JK FF Characteristic Table
JK FF Characteristic Equation
Race around condition:
If J = K = 1, output continuously
toggles. To avoid race around
condition, use edge triggering or
master slave FF

18. JK FF Excitation Table
JK FF Characteristic Table
JK FF Excitation Table
JK FF StateDiagram

19. T Flip-Flop
Is a modification of JK FF. Obtained from JK FF by
connecting both the inputs, J and K to 1.
T FF using NAND gates
T FF using NOR gates

20. T FF Function Table T FF Characteristic Table
T FF Characteristic Equation
T FF Excitation Table

21. ExcitationTable
Is derived from the characteristic Table.This Table consists of present state, next state and inputs.
The Table is used in the Synchronous Sequential CircuitDesign.
T
D
SR
JK

22. Master Slave Flip-Flop
• Is constructed from two FF; one acts as the master and the
otherslave
• Master is positive level triggered and slaveis negative level
triggered
• Master FF output is connected to the input of the slave FF

23. Master Slave Flip-Flop
Logic Symbol
Logic Diagram

24. 1. Realize D FF using SR FF
• Write the characteristic table of D FF.
• Write the excitation table of SR FF
• Determine the expressions for the given FF inputs using
K-Map Draw the FF conversion logic diagram
D FF Characteristic Table
Realization of a FF using other Flip-flops

25. 2. Realize T FF using D FF
D FF Excitation Table
Flip-flop Conversion Diagram

26. 3. Realize JK FF using D FF
D FF Excitation Table
Logic Diagram

27. Synchronous Sequential Circuit is analyzed and designed with the
help of two models.
1.Mealy model
2.Moore model
Analysis of Clocked Sequential Circuits

28. 1. Analyze the given D Flip-flop equations:
DA = xQA+ QB ; DB = Q’AQB y = x’Q’B + xQA
Steps:
i)Determine FF input equations in terms of input variables and present state.
ii)Determine next state equation of FF using characteristic table.
iii)Determine circuit output if it is present.
Characteristic Table
In function table, Next States are filled by using characteristic table of the
corresponding FF.
Function Table

29. State table consists of present state, next state and output
State Diagram
State Table

30. Design of Clocked Synchronous Sequential
Circuit
Design Procedure:
i. A state diagram is given which describes the behavior of the circuit
that is
to be designed.
ii. Obtain the state table
iii. Reduce the number of states by state reduction method, if required.
iv. Do state assignment, if required.
v. Determine the FF required and assign the letter symbols
vi. Decide the type of FF to be used.
vii.Derive the circuit excitation table from the state table
viii.Obtain the expression for circuit output and flip flop output
ix. Implement the logic diagram
1.Design the Synchronous Sequential Circuit for Melay state
diagram using JK Flip-flop
State Table
Excitation Table
Transition Table

31. K-Map for Flip-flops

33. STATE DIAGRAM
State Reduction or State Minimization, State Assignment

34. STATETABLE –REDUCTION

35. Reduced STATETABLE
Reduced STATE DIAGRAM

36. COUNTER
• Counter is a sequential circuit.
• A digital circuit which is used for a counting pulses is known counter.
• Counter is the widest application of flip-flops.
• It is a group of flip-flops with a clock signal applied.
APPLICATIONS OF COUNTER

37. COUNTERSTYPES

38. Asynchronous vs Synchronous Counter

40. Asynchronous Counter (4-Bit)
Timing Diagram of 4-bit
Ripple counter
Truth Table of Asynchronous
Counter

41. 3-bit Asynchronous Down Counter (Mod-8 Counter)
Timing Diagram
Truth Table

42. Mod-10 Ripple Counter (Decade Counter or BCD
Counter)
Truth Table
Timing Diagram

43. • Mod-5 Counter counts 5 states from 000 to 100.
• Three FFs are needed in this design NAND gate output is connected to Reset input of all the FFs
• During the fifth state, all the FFs are in Reset condition. Truth Table
Timing Diagram
Mod-5 Ripple Counter

44. 4-bit Asynchronous Up/ Down Counter
Truth Table

45. Synchronous Counter
A counter is a register capable of counting the number of clock pulses arriving at its clock input.
Count represents the number of clock pulses arrived

46. BINARY COUNTER/ SYNCHRONOUS COUNTER / UP
COUNTER

47. Ring Counter
Truth Table of a Ring Counter

48. Johnson Counter/Twisted Ring Counter
Function Table of Johnson Counter

49. 1.Design a synchronous Mod-6 counter using JK FF.
State Diagram
SYNCHRONOUS COUNTER DESIGN

52. HOME WORK /PRACTICE
1. Design a synchronous decade counter using T FF
2. Design a 3-bit synchronous counter using JK FF.
3. Design a synchronous Mod-5 counter using T FF.
4. Design a synchronous counter to count the sequence 0,1,3,4,5,7,0,…using D FF.

53. REGISTER

54. SHIFT REGISTER
Applications:
Serial to Parallel Convertor
Parallel to Serial Convertor
Shift Register Counters
Ring Counter
Johnson Counter
Pseudo Random Sequence Generator

55. Serial In and Serial Out Shift Register
Serial In and Parallel Out Shift Register

56. Parallel In and Serial Out Shift Register
Parallel In and Parallel Out Shift Register
No of positive
edge of
Clock A B C D
Serial
out
0 0 1 1 0 -
1 - 0 1 1 0
2 - - 0 1 1
3 - - - 0 1
4 - - - - 0

57. Universal Shift Register
Function Table of Universal Shift Register

58. STAY HOME…
STAY SAFE…