Track B- Advanced ESL verification - Mentor


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  • Dynamic bandwidth means that static analysis methods are not sufficientLarger code footprint –> higher miss ratio
  • People have been creating virtual prototypes for years, but many did not have a model that is highly correlated to the hardware architecture. We have taken an architecture model and package it such that it can run very efficiently in a software environment. If timing and power is not needed, you should be able to run only the functional model against the software at a very high speed. But when timing is needed, you should be able to turn timing on and run the software against the TLM more accurate timing layer. In most cases, timing will be required if you want to tune the software to optimize the performance and the power of your design in the context of the application software.
  • With Vista, we propose a hardware-aware virtual prototype that in addition to modeling the functional aspects of the hardware can also model the timing and power attributes. The de-facto modeling standard today are the SystemC and TLM-2.0, essentially C/C++ class libraries that add concurrency, timing,and communication on top of C/C++. As a side note, it is of value having both hardware and software driven from a single language and abstraction. with the emerging C/C++ and SystemC synthesis technologies, a virtual platform will become essentially a golden reference for the downstream implementation.It is important to say however that a Virtual Prototype will not replace the current physical prototype methods, but will allow earlier integration of software and in many cases better visibility into functional execution and timing/power profiles before the hardware is available.
  • Users can link with a Virtual Prototype with physical devices such as terminals, displays, USB and Ethernet i/o’s through the host driver and run the Virtual Model under realistic environment conditions.
  • In the cases that the RTL is large and simulates large number of events resulting from software execution, users can run the Veloce accelerator to run the RTL several orders of magnitude after. In this case {see slide).
  • Track B- Advanced ESL verification - Mentor

    1. 1. Advanced ESL Verification Refinement – From ESL to RTL <br />Guy Moshe<br />General Manager<br />DCS<br />Mentor Graphics<br />May 4, 2011<br />
    2. 2. Abstract<br />ESL is quickly evolving as a methodology for designing a system using abstraction above RTL. This session covers an ESL Verification flow describing how ESL can be used to validate the HW/SW functionality, performance and power requirements.  In addition, it addresses how the ESL environment can be reused at the SoC RTL block level verification phase, and at the system integration phase using emulation.<br />Advanced ESL Verification Refinement <br />
    3. 3. Trends – Design Complexity Explosion<br />Co Processor<br />Video<br />Processors<br />Interconnect Fabric<br />INTC<br />DMA<br />USB<br />ETHERNET<br />FLASH<br />DDR<br />Peripherals<br />ADC<br />WD<br />TIMER<br />UART<br />15 billion connected devices by 2015 <br />Basic+ Smart+ Enhanced phones<br />Mobile processor clock speed > 1 GHz (32 nm)<br />Highly integrated: Audio, video, 3D graphics, text<br />Requires long battery life <br />Marvell’s ARMADA 628 SoC<br />Used for smartphones and tablets <br />1.5 GHz tri-core processor <br />Dual stream 1080p 3D video <br />3D graphics performance (200M triangles/sec)<br />Ultra-low-power, long battery life<br />2 billion phones by 2012<br />Advanced ESL Verification Refinement <br />
    4. 4. Design and Verification is a Struggle …<br />It’s a design and verification struggle<br />It’s a power struggle<br />Source: The International Technology Roadmap for Semiconductors (ITRS), 2008 Update)<br />Power requirement vs. power trends<br />Cost of design tasks per technology<br />Advanced ESL Verification Refinement <br />
    5. 5. A Closer look on Multi-core Challenges<br />Video<br />Accelerator<br />CORE<br />CORE<br />Cache control<br />I/cache<br />D/cache<br />I/cache<br />D/cache<br />DDR<br />INTC<br />DMA<br />USB<br />ETHERNET<br />FLASH<br />Peripherals<br />ADC<br />WD<br />TIMER<br />UART<br />DDR2<br />DDR2<br />ETH<br />Multi-core architectures offer higher multi-tasking performance but introduce new design challenges<br />Scale for best MIPS per Watt<br />Caching strategy<br />Port and Tune firmware and operating system to the target hardware<br />Migrate single-threaded applications to multi-core <br />Balance HW and SW loads<br />Designers need a platform that enable fast compilation and configuration cycles through software and hardware alternatives <br />Software<br />Interconnect Fabric<br />Advanced ESL Verification Refinement <br />
    6. 6. Introducing ESL Methodology<br />Algorithmic<br />1 Sec<br />TLM<br />Simulation Time Example<br />RTL<br />GATE<br />1 Day<br />Electronic System Level (ESL): A set of electronic hardware/software design methodologies using abstraction above RTL for designing systems on chips (SoCs), FPGAs and boards<br />ESL allows you to reduce verification effort by:<br />Fast simulation of the design functional spec in the system’s context<br />Reducing RTL Verification effort by finding bugs early<br />Validating Software integration with hardware even before RTL<br />Reducing RTL block verification by using high level synthesis<br />Advanced ESL Verification Refinement <br />
    7. 7. ESL Verification Flow – Why?<br />Transaction-level models (TLM) allow designers to:<br />Build software development and hardware architecture exploration platforms before committing to RTL.<br />Manage the complexity of sophisticated large-scale SoC<br />Build and verify SoCs more quickly<br />Run orders of magnitude faster than RTL <br />Reuse the TLM as RTL verification testbench component<br />Standards-driven: OSCI TLM, SystemC, C++, OVM, UVM SystemVerilog<br />Advanced ESL Verification Refinement <br />
    8. 8. TLM System Verification:Validating & Debugging the SoC<br />Video<br />Accelerator<br />CORE<br />DDR<br />INTC<br />DMA<br />USB<br />ETHERNET<br />FLASH<br />Peripherals<br />ADC<br />WD<br />TIMER<br />UART<br />Verify Architecture and System Behavior<br />Integrated Behavior<br />System Level scenarios <br />SW Driven Tests<br />Data Driven Tests<br />Debug and comprehend your System<br />TLM code view<br />Process view<br />Transaction View<br />Event Tracing<br />Memory Profiling<br />Interconnect Fabric<br />Verify Architecture to Meet the Design Functional Spec<br />Advanced ESL Verification Refinement <br />
    9. 9. Architecting and Optimizing For Performance And Power <br />Video<br />Accelerator<br />CORE<br />CORE<br />Cache control<br />I/cache<br />D/cache<br />I/cache<br />D/cache<br />DDR<br />INTC<br />DMA<br />USB<br />ETHERNET<br />FLASH<br />Peripherals<br />ADC<br />WD<br />TIMER<br />UART<br />DDR2<br />DDR2<br />ETH<br />Partition HW & SW<br />Define Bus layering & arbitration<br />Define Cache & Memories layering & sizing<br />Optimize Data throughput and latencies<br />Analyze Power Profiles / Distribution <br />Interconnect Fabric<br />Advanced ESL Verification Refinement <br />
    10. 10. Software Hardware Interaction Critical<br />Advanced ESL Verification Refinement <br />Video<br />Accelerator<br />CORE<br />CORE<br />Cache control<br />I/cache<br />D/cache<br />I/cache<br />D/cache<br />DDR<br />INTC<br />DMA<br />USB<br />ETHERNET<br />FLASH<br />Peripherals<br />ADC<br />WD<br />TIMER<br />UART<br />DDR2<br />DDR2<br />ETH<br />App.<br /><ul><li>Multi-core architecture presents much tighter hardware software dependencies
    11. 11. Multiple applications may run with different performance and power profiles
    12. 12. Dynamic Bandwidth requirements
    13. 13. The Mapping technique of application threads to the cores will impact performance and power
    14. 14. Different code footprint depending on number of cores</li></ul>App.<br />App<br />Operating System<br />Interconnect Fabric<br />
    15. 15. HW/SW Tradeoff Analysis<br />Video<br />Accelerator<br />ISS<br />Peripherals<br />ADC<br />WD<br />TIMER<br />UART<br /><ul><li>C/C++ execution on processor vs. HW acceleration
    16. 16. Common HW and SW representation (C/C++)
    17. 17. Explore power and timing affects in the System Context</li></ul>DDR<br />INTC<br />DMA<br />USB<br />Controller<br />ETHERNET<br />FLASH<br />App<br />OS<br />FW<br />DDR2<br />DDR2<br />ETH<br />USB<br />HW Database<br />Advanced ESL Verification Refinement <br />
    18. 18. End User<br />Application<br />Software<br />ROM<br />CPU<br />CPU AXI I/F<br />AXI Bus<br />Virtual <br />Prototype<br />JPEG<br />Encoder<br />FPU<br />RAM<br />Performance<br />Software Debuggers<br /> (GDB, ARM, EDGE)<br />Power<br />Transaction Level Platform<br />Creating a Virtual Prototype<br />Delivers a target HW model executable to the software team <br />Integrate final application software against actual hardware architecture<br />Validate and debug software against early HW model before RTL<br />Tune software to meet performance and power requirements<br />Advanced ESL Verification Refinement <br />
    19. 19. Running The Virtual Platform<br />Video<br />Accelerator<br />ISS<br />Peripherals<br />ADC<br />WD<br />TIMER<br />UART<br />SW IDE<br />DDR<br />INTC<br />DMA<br />USB<br />Controller<br />ETHERNET<br />FLASH<br />App<br />OS<br />FW<br />HW Access & Analysis<br />DDR2<br />DDR2<br />ETH<br />USB<br />HW Database<br />HW / SW Partitioning Exploration<br />Advanced ESL Verification Refinement <br />
    20. 20. Physical I/O <br />Video<br />Accelerator<br />ISS<br />Peripherals<br />ADC<br />WD<br />TIMER<br />UART<br /><ul><li>Connect Virtual Model to physical I/O
    21. 21. USB, LAN IP
    22. 22. Realistic packet load generation</li></ul>USB App<br />USB Driver<br />DDR<br />INTC<br />DMA<br />USB<br />Controller<br />ETHERNET<br />FLASH<br />USB App<br />DDR2<br />DDR2<br />ETH<br />USB<br />USB Driver<br />Host PC<br />USB<br />Controller<br />Driver<br />Advanced ESL Verification Refinement <br />
    23. 23. SW engineer Use Case for multi-core <br />Explore various cache configurations<br />Explore various software parallelization techniques<br />Early test of data regularity for optimized cache access<br />Early-stage power estimation for most efficient thread partitioning<br />Video<br />Accelerator<br />ISS<br />Peripherals<br />ADC<br />WD<br />TIMER<br />UART<br />Single Core<br />DDR<br />INTC<br />DMA<br />USB<br />Controller<br />ETHERNET<br />FLASH<br />App<br />OS<br />FW<br />DDR2<br />DDR2<br />ETH<br />USB<br />Dual Core<br />HW Database<br />Advanced ESL Verification Refinement <br />
    24. 24. TSMC ESL to RTL SoC Verification Vision<br />Advanced ESL Verification Refinement <br />
    25. 25. TLM ARM Cortext-A9 platform<br />Advanced ESL Verification Refinement <br />UART<br />MPEG<br />Drivers<br />Linux<br />Cortex-A9<br />
    26. 26. UART<br />MPEG<br />Cortex-A9<br />TLM Platform with Power<br />Advanced ESL Verification Refinement <br />TLM Domain Shut Down<br />Power<br />TSMC<br />iPPA<br />Engine<br />Show CPU Voltage/ Frequency Scaling<br />
    27. 27. TLM/RTL Hybrid Platform <br />Advanced ESL Verification Refinement <br />Synthesized to RTL<br />SC/SV<br />Connection<br />AXI<br />Transactors<br />MPEG<br />RTL<br />UART<br />RTL<br />Transactor<br />Hybrid Extended Platform<br />
    28. 28. TLM Design<br />Interrupt<br />Controller<br />Vista<br />Veloce<br />RTL Design<br />AXI<br />xMVC<br />Cortex A9<br />ISS/TLM<br />(multi-core)<br />MPEG<br />AXI Bridge <br />RTL<br />MPEG<br />RTL<br />AXI Bus TLM<br />Signal Level AXI Bus<br />Memory<br />TLM<br />I/O<br />Subsystem<br />ESL Verification: From ESL to Acceleration<br />Mixed TLM with accelerated RTL design <br />RTL runs on Emulation at MHz speeds<br />Software runs on Multi-core Cortex A9 TLM model at 200 MIPS<br />Fast extended platform for validating SW against accelerated & accurate HW model<br />Advanced ESL Verification Refinement <br />RTL Debug<br />Software<br />SW Debug<br />TLM Debug<br />20<br />
    29. 29. Hybrid TLM Platform with RTL Emulation<br />Advanced ESL Verification Refinement <br />Accelerated<br />On Emulation<br />VGA<br />ADAPTER<br />RTL?<br />SC/SV<br />MPEG<br />RTL<br />Uses AXI<br />xMVC<br />Hybrid Extended Platform<br />Linux<br />
    30. 30. Reusing TLM Models for OVM/UVM Block Verification<br />Advanced ESL Verification Refinement <br />
    31. 31. UART<br />MPEG<br />Cortex-A9<br />Virtual Prototype w Linux<br />Advanced ESL Verification Refinement <br />Link SW Dev Tool<br />Link Linux<br />Virtual <br />Prototype<br />
    32. 32. Summary<br />We have presented ESL methodology that enables<br />Creation of TLM Platforms<br />Virtual Prototyping and Software integration<br />Fast simulation speeds<br />Power Performance optimization<br />TLM verification at the system level<br />TLM/RTL refinement verification<br />We have presented a demonstration of ARM based reference flow<br />ESL and TLM will enable efficient design and prototyping of any future low-power multi-core SoC’s<br />Advanced ESL Verification Refinement <br />