1. Advanced ESL Verification Refinement – From ESL to RTL Guy Moshe General Manager DCS Mentor Graphics May 4, 2011
2. Abstract ESL is quickly evolving as a methodology for designing a system using abstraction above RTL. This session covers an ESL Verification flow describing how ESL can be used to validate the HW/SW functionality, performance and power requirements. In addition, it addresses how the ESL environment can be reused at the SoC RTL block level verification phase, and at the system integration phase using emulation. Advanced ESL Verification Refinement
3. Trends – Design Complexity Explosion Co Processor Video Processors Interconnect Fabric INTC DMA USB ETHERNET FLASH DDR Peripherals ADC WD TIMER UART 15 billion connected devices by 2015 Basic+ Smart+ Enhanced phones Mobile processor clock speed > 1 GHz (32 nm) Highly integrated: Audio, video, 3D graphics, text Requires long battery life Marvell’s ARMADA 628 SoC Used for smartphones and tablets 1.5 GHz tri-core processor Dual stream 1080p 3D video 3D graphics performance (200M triangles/sec) Ultra-low-power, long battery life 2 billion phones by 2012 Advanced ESL Verification Refinement
4. Design and Verification is a Struggle … It’s a design and verification struggle It’s a power struggle Source: The International Technology Roadmap for Semiconductors (ITRS), 2008 Update) Power requirement vs. power trends Cost of design tasks per technology Advanced ESL Verification Refinement
5. A Closer look on Multi-core Challenges Video Accelerator CORE CORE Cache control I/cache D/cache I/cache D/cache DDR INTC DMA USB ETHERNET FLASH Peripherals ADC WD TIMER UART DDR2 DDR2 ETH Multi-core architectures offer higher multi-tasking performance but introduce new design challenges Scale for best MIPS per Watt Caching strategy Port and Tune firmware and operating system to the target hardware Migrate single-threaded applications to multi-core Balance HW and SW loads Designers need a platform that enable fast compilation and configuration cycles through software and hardware alternatives Software Interconnect Fabric Advanced ESL Verification Refinement
6. Introducing ESL Methodology Algorithmic 1 Sec TLM Simulation Time Example RTL GATE 1 Day Electronic System Level (ESL): A set of electronic hardware/software design methodologies using abstraction above RTL for designing systems on chips (SoCs), FPGAs and boards ESL allows you to reduce verification effort by: Fast simulation of the design functional spec in the system’s context Reducing RTL Verification effort by finding bugs early Validating Software integration with hardware even before RTL Reducing RTL block verification by using high level synthesis Advanced ESL Verification Refinement
7. ESL Verification Flow – Why? Transaction-level models (TLM) allow designers to: Build software development and hardware architecture exploration platforms before committing to RTL. Manage the complexity of sophisticated large-scale SoC Build and verify SoCs more quickly Run orders of magnitude faster than RTL Reuse the TLM as RTL verification testbench component Standards-driven: OSCI TLM, SystemC, C++, OVM, UVM SystemVerilog Advanced ESL Verification Refinement
8. TLM System Verification:Validating & Debugging the SoC Video Accelerator CORE DDR INTC DMA USB ETHERNET FLASH Peripherals ADC WD TIMER UART Verify Architecture and System Behavior Integrated Behavior System Level scenarios SW Driven Tests Data Driven Tests Debug and comprehend your System TLM code view Process view Transaction View Event Tracing Memory Profiling Interconnect Fabric Verify Architecture to Meet the Design Functional Spec Advanced ESL Verification Refinement
9. Architecting and Optimizing For Performance And Power Video Accelerator CORE CORE Cache control I/cache D/cache I/cache D/cache DDR INTC DMA USB ETHERNET FLASH Peripherals ADC WD TIMER UART DDR2 DDR2 ETH Partition HW & SW Define Bus layering & arbitration Define Cache & Memories layering & sizing Optimize Data throughput and latencies Analyze Power Profiles / Distribution Interconnect Fabric Advanced ESL Verification Refinement
17. Explore power and timing affects in the System ContextDDR INTC DMA USB Controller ETHERNET FLASH App OS FW DDR2 DDR2 ETH USB HW Database Advanced ESL Verification Refinement
18. End User Application Software ROM CPU CPU AXI I/F AXI Bus Virtual Prototype JPEG Encoder FPU RAM Performance Software Debuggers (GDB, ARM, EDGE) Power Transaction Level Platform Creating a Virtual Prototype Delivers a target HW model executable to the software team Integrate final application software against actual hardware architecture Validate and debug software against early HW model before RTL Tune software to meet performance and power requirements Advanced ESL Verification Refinement
19. Running The Virtual Platform Video Accelerator ISS Peripherals ADC WD TIMER UART SW IDE DDR INTC DMA USB Controller ETHERNET FLASH App OS FW HW Access & Analysis DDR2 DDR2 ETH USB HW Database HW / SW Partitioning Exploration Advanced ESL Verification Refinement
22. Realistic packet load generationUSB App USB Driver DDR INTC DMA USB Controller ETHERNET FLASH USB App DDR2 DDR2 ETH USB USB Driver Host PC USB Controller Driver Advanced ESL Verification Refinement
23. SW engineer Use Case for multi-core Explore various cache configurations Explore various software parallelization techniques Early test of data regularity for optimized cache access Early-stage power estimation for most efficient thread partitioning Video Accelerator ISS Peripherals ADC WD TIMER UART Single Core DDR INTC DMA USB Controller ETHERNET FLASH App OS FW DDR2 DDR2 ETH USB Dual Core HW Database Advanced ESL Verification Refinement
25. TLM ARM Cortext-A9 platform Advanced ESL Verification Refinement UART MPEG Drivers Linux Cortex-A9
26. UART MPEG Cortex-A9 TLM Platform with Power Advanced ESL Verification Refinement TLM Domain Shut Down Power TSMC iPPA Engine Show CPU Voltage/ Frequency Scaling
31. UART MPEG Cortex-A9 Virtual Prototype w Linux Advanced ESL Verification Refinement Link SW Dev Tool Link Linux Virtual Prototype
32. Summary We have presented ESL methodology that enables Creation of TLM Platforms Virtual Prototyping and Software integration Fast simulation speeds Power Performance optimization TLM verification at the system level TLM/RTL refinement verification We have presented a demonstration of ARM based reference flow ESL and TLM will enable efficient design and prototyping of any future low-power multi-core SoC’s Advanced ESL Verification Refinement
Editor's Notes
Dynamic bandwidth means that static analysis methods are not sufficientLarger code footprint –> higher miss ratio
People have been creating virtual prototypes for years, but many did not have a model that is highly correlated to the hardware architecture. We have taken an architecture model and package it such that it can run very efficiently in a software environment. If timing and power is not needed, you should be able to run only the functional model against the software at a very high speed. But when timing is needed, you should be able to turn timing on and run the software against the TLM more accurate timing layer. In most cases, timing will be required if you want to tune the software to optimize the performance and the power of your design in the context of the application software.
With Vista, we propose a hardware-aware virtual prototype that in addition to modeling the functional aspects of the hardware can also model the timing and power attributes. The de-facto modeling standard today are the SystemC and TLM-2.0, essentially C/C++ class libraries that add concurrency, timing,and communication on top of C/C++. As a side note, it is of value having both hardware and software driven from a single language and abstraction. with the emerging C/C++ and SystemC synthesis technologies, a virtual platform will become essentially a golden reference for the downstream implementation.It is important to say however that a Virtual Prototype will not replace the current physical prototype methods, but will allow earlier integration of software and in many cases better visibility into functional execution and timing/power profiles before the hardware is available.
Users can link with a Virtual Prototype with physical devices such as terminals, displays, USB and Ethernet i/o’s through the host driver and run the Virtual Model under realistic environment conditions.
In the cases that the RTL is large and simulates large number of events resulting from software execution, users can run the Veloce accelerator to run the RTL several orders of magnitude after. In this case {see slide).
