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From Software Based Verification  to Firmware Development Ireneusz Sobański Evatronix SA
Outline <ul><li>About Evatronix </li></ul><ul><li>Hardware/Software Convergence </li></ul><ul><li>USB Mass Storage Applica...
Company Overview <ul><li>Set up in 1997, over a dozen years of IP experience </li></ul><ul><li>Over 400 successful silicon...
Demands for SoC <ul><li>Users expect interface flexibility </li></ul><ul><ul><li>Communication Devices (Ethernet, Bluetoot...
Hardware/Software Convergence <ul><li>Hardware/software meeting </li></ul><ul><ul><li>Software plays the glue logic role (...
External hard disk example <ul><li>Microprocessor </li></ul><ul><li>USB Protocol layer </li></ul><ul><li>USB PHY layer </l...
TB Environment Overview <ul><li>General objectives </li></ul><ul><ul><li>Support for virtual prototyping (TLM Model) </li>...
TB Architecture  (SystemC)
Software Based Verification <ul><li>Drive & test DUT with (ANSI) C functions </li></ul><ul><ul><li>Provides functional ver...
TB  Environment issues <ul><li>Mimic CPU mechanisms  </li></ul><ul><ul><li>program/interrupts switching </li></ul></ul><ul...
Software Tests Architecture Regs Access USB Endpoint Data USB Framework Test (randomization, configuration, direct tests) ...
Firmware Development <ul><li>USBSS Mass Storage Firmware </li></ul><ul><ul><li>USB device registers access  (USB HAL) </li...
Firmware Architecture Regs Access USB Endpoint Data USB Mass  Storage Class USB Device Framework Disk Abstraction Layer Fi...
Summary <ul><li>Use of C in verification process is not a new idea </li></ul><ul><li>Software based verification brings ne...
Thank You [email_address] www.evatronix-ip.com
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Evatronix track h

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Evatronix track h

  1. 1. From Software Based Verification to Firmware Development Ireneusz Sobański Evatronix SA
  2. 2. Outline <ul><li>About Evatronix </li></ul><ul><li>Hardware/Software Convergence </li></ul><ul><li>USB Mass Storage Application </li></ul><ul><li>Test Bench Environment Overview </li></ul><ul><li>Software Based Verification </li></ul><ul><li>Firmware Development </li></ul><ul><li>Summary </li></ul>
  3. 3. Company Overview <ul><li>Set up in 1997, over a dozen years of IP experience </li></ul><ul><li>Over 400 successful silicon designs to date </li></ul><ul><li>More than 30 products in the IP catalog </li></ul><ul><ul><li>8051, USB, NAND Flash, SDIO, Multimedia </li></ul></ul><ul><li>70+ experienced engineers </li></ul><ul><li>Member of many technical organizations </li></ul><ul><ul><li>USB-IF, SD Card Association, OCP-IP and other </li></ul></ul><ul><li>Active participation in European projects </li></ul>
  4. 4. Demands for SoC <ul><li>Users expect interface flexibility </li></ul><ul><ul><li>Communication Devices (Ethernet, Bluetooth, …) </li></ul></ul><ul><ul><li>Peripheral Devices (USB, SDIO, SPI, …) </li></ul></ul><ul><ul><li>Mass Storage (HDD, Flash, …) </li></ul></ul><ul><li>Applications need computational power </li></ul><ul><ul><li>Display Acceleration (MPEG, 3D, …) </li></ul></ul><ul><ul><li>Cryptographic Devices (3DES, AES, …) </li></ul></ul><ul><li>SoC suppliers must balance the cost (M$) </li></ul><ul><ul><li>One SoC – many applications </li></ul></ul><ul><ul><li>More functionality goes to software </li></ul></ul><ul><ul><li>(RT)OS gain in popularity (flexibility & cost !) </li></ul></ul>
  5. 5. Hardware/Software Convergence <ul><li>Hardware/software meeting </li></ul><ul><ul><li>Software plays the glue logic role (communication) </li></ul></ul><ul><ul><li>Hardware accelerates software routines (computation) </li></ul></ul><ul><ul><li>In both cases every IP needs a DRIVER! </li></ul></ul><ul><li>Requirements for IP provider </li></ul><ul><ul><li>Drivers become the integral part of the hardware IP </li></ul></ul><ul><ul><li>Integration verification facilities (integration tests) </li></ul></ul><ul><ul><li>Support for virtual prototyping (TLM models) </li></ul></ul>
  6. 6. External hard disk example <ul><li>Microprocessor </li></ul><ul><li>USB Protocol layer </li></ul><ul><li>USB PHY layer </li></ul><ul><li>SATA device </li></ul><ul><li>USB HAL </li></ul><ul><li>USB Framework </li></ul><ul><li>USB Mass Storage Layer </li></ul><ul><li>SATA Stack </li></ul>Software Stack
  7. 7. TB Environment Overview <ul><li>General objectives </li></ul><ul><ul><li>Support for virtual prototyping (TLM Model) </li></ul></ul><ul><ul><li>Layered architecture (link/protocol/…) </li></ul></ul><ul><ul><li>Extensive usage of randomization </li></ul></ul><ul><ul><li>Self checking testbench </li></ul></ul><ul><ul><li>Functional coverage </li></ul></ul><ul><li>Further goals </li></ul><ul><ul><li>Early software development (before FPGA) </li></ul></ul><ul><ul><li>Software based tests (reused on prototyping) </li></ul></ul>
  8. 8. TB Architecture (SystemC)
  9. 9. Software Based Verification <ul><li>Drive & test DUT with (ANSI) C functions </li></ul><ul><ul><li>Provides functional verification of the DUT </li></ul></ul><ul><ul><li>By default runs in native mode (on the PC) </li></ul></ul><ul><ul><li>ANSI C guarantees portability </li></ul></ul><ul><li>Reuse in an FPGA prototype </li></ul><ul><ul><li>Can be compiled for the CPU (real device) </li></ul></ul><ul><ul><li>Some tests may be reused at this stage </li></ul></ul><ul><li>Reuse at the system integrator’s site </li></ul><ul><ul><li>Can be compiled for the CPU (ISS model) </li></ul></ul><ul><ul><li>Simplify tests reuse </li></ul></ul>
  10. 10. TB Environment issues <ul><li>Mimic CPU mechanisms </li></ul><ul><ul><li>program/interrupts switching </li></ul></ul><ul><li>Choose memory modeling method </li></ul><ul><ul><li>physical memory/memory model </li></ul></ul><ul><li>Define DUT access through macros </li></ul><ul><ul><li>Access through address / function call </li></ul></ul><ul><li>Assign portable layers </li></ul><ul><ul><li>Hardware Abstraction Layer for device management </li></ul></ul><ul><li>Manage randomization routines </li></ul><ul><ul><li>All SCV (SystemC) must be outside of the HAL </li></ul></ul>
  11. 11. Software Tests Architecture Regs Access USB Endpoint Data USB Framework Test (randomization, configuration, direct tests) Interrupts Regs Access CPU (switch) MEM (physical memory) OCP-IP OCP-IP SystemC SystemC USB Host
  12. 12. Firmware Development <ul><li>USBSS Mass Storage Firmware </li></ul><ul><ul><li>USB device registers access (USB HAL) </li></ul></ul><ul><ul><li>USB endpoint data manipulation (USB HAL) </li></ul></ul><ul><ul><li>USB framework (USB Stack) </li></ul></ul><ul><ul><li>USB Mass Storage Class (Firmware) </li></ul></ul><ul><ul><li>Disk abstraction layer (Disk HAL) </li></ul></ul><ul><ul><ul><li>RAM disk (emulation functions) </li></ul></ul></ul><ul><ul><ul><li>ATA device driver (ATA HAL) </li></ul></ul></ul><ul><li>Software development flow </li></ul><ul><ul><li>Start i n a virtual prototype (in verification environment) </li></ul></ul><ul><ul><li>Finish i n an FPGA prototype (with single modifications) </li></ul></ul>
  13. 13. Firmware Architecture Regs Access USB Endpoint Data USB Mass Storage Class USB Device Framework Disk Abstraction Layer Firmware (main) RAM Disk emulation SATA Stack Regs Acc.. USB SS -DEV RAM ATA-IF
  14. 14. Summary <ul><li>Use of C in verification process is not a new idea </li></ul><ul><li>Software based verification brings new benefits </li></ul><ul><ul><li>The same tests for TLM/RTL/FPGA prototype… </li></ul></ul><ul><li>Not everything is ideal </li></ul><ul><ul><li>Perfect for normal work, but not for corners </li></ul></ul><ul><ul><li>Randomization must be done carefully </li></ul></ul><ul><li>Good starting point for software development </li></ul><ul><ul><li>Basic tests could be run in an FPGA prototype </li></ul></ul><ul><ul><li>Hardware Abstraction Layer is fully reusable </li></ul></ul><ul><ul><li>The firmware is truly verified and ahead of schedule </li></ul></ul>
  15. 15. Thank You [email_address] www.evatronix-ip.com

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