22/04/13 Valid for use model with centralized register banks as well
22/04/13 Valid for use model with centralized register banks as well
22/04/13 The generator can look at all of the constraints that affect a specific field, and if the constraints are solvable, it will randomly pick a value for the field based on the range of possible solutions that satisfy all of the rules. If there is no possible solution, this causes a generation contradiction. For example, A > 5 and A < 5 is not solvable.
22/04/13 Basic constraint types: keep boolean-expr ; Constrain boolean-expr to be TRUE keep for each ( item ) in list-name; Applies constraints to items in a list We can use the implicit index variable for referencing the current item in the list
Apr 22, 2013
Apr 22, 2013
Generic and Automatic Specman Based Verification Environment
Imaging DivisionImaging DivisionST MicroelectronicsST MicroelectronicsGENERIC AND AUTOMATIC SPECMANGENERIC AND AUTOMATIC SPECMANBASED VERIFICATION ENVIRONMENT FORBASED VERIFICATION ENVIRONMENT FORIMAGE SIGNAL PROCESSING IPsIMAGE SIGNAL PROCESSING IPsAbhishek JainAbhishek Jain
Imaging DivisionImaging DivisionST MicroelectronicsST MicroelectronicsIntroductionIntroductionImage signal processing IP’s …Image signal processing algorithms are developed and evaluatedusing ‘C’/Python before RTL implementation.‘C’/Nathair(Python) models are used as a golden model for the IP developmentThe common bus protocols are defined for internal register and data transfers.A pool of configurable image signal processing IP modules are assembledtogether to satisfy a wide range of complex video processing SoCs.
Imaging DivisionImaging DivisionST MicroelectronicsST MicroelectronicsInterfaces of image signalInterfaces of image signalprocessing IPprocessing IPImage SignalProcessing IP(RTL)NInput video datainterfacesSOutputInterruptsQRegisterInterfaces(T1 interface)TOutput videodata interfacesMMemoryinterfaces
Imaging DivisionImaging DivisionST MicroelectronicsST MicroelectronicsGeneric VerificationGeneric VerificationEnvironmentEnvironmentBasic blocks of Generic Verification …Q instances of register interface eVC(Everest eVC) agents are used forregister interface.P (P = max (N,T)) instances of video data interface eVC(IDP/VDB/RG/ISB)agents are used for video data interface.S instances of interrupt checker and M instances of memory model areused to interface with a DUT.
Imaging DivisionImaging DivisionST MicroelectronicsST MicroelectronicsBasic blocks of GenericBasic blocks of GenericVerificationVerificationImageSignalProcessingIP(DUT)VideoData BusinterfaceeVC(IDP/VDB/RG/ISB)vr_adRegisterModelMemory ModelRegisterBusinterfaceeVC(Everest)Apply /CollectTestVectorsTest EnvironmentApply /CollectTestVectors
Imaging DivisionImaging DivisionST MicroelectronicsST MicroelectronicsIDP instantiation within a ‘wrapper’ unit.IDP instantiation within a ‘wrapper’ unit.sys‘wrapper’ unitdata checking unitMandatoryidp_wrapperIdp internal structureScoreboardsst_idp_env
Imaging DivisionImaging DivisionST MicroelectronicsST MicroelectronicsGeneric and Automatic VerificationGeneric and Automatic VerificationEnvironmentEnvironmentTest cases for registers and video data interface(s).IP-XACT API clients are used for generation of IP specific files.In Generic Verification Environment, Following the IP specific filesRegister description file for ‘vr_ad’ register model.Configuration files to configure the eVC’s.Constraint file to generate constrained random data sequences.Functional Coverage file.Data checker file to compare the output of IP with output of‘C’/Nathair model and
Imaging DivisionImaging DivisionST MicroelectronicsST MicroelectronicsSpirit : OverviewSpirit : OverviewSPIRIT stands for“Structure for Packaging, Integrating and Re-using IP within Tool-flows”Standard based on XML open formatDescribes :Register MapBus InterfacesTop-level I/OOthers including interconnect, constraints, …
Imaging DivisionImaging DivisionST MicroelectronicsST Microelectronicsspec2verilog - used to convert a mif/docx filespec2verilog - used to convert a mif/docx fileinto verilog and xml filesinto verilog and xml filesSYNOPSIS :spec2verilog.sh -file <file-name>.mif/docx [-out <XMLFileName>.xml] [-log <logName>.log] [-inter] [-version]DESCRIPTIONspec2verilog converts a .MIF/.docx file describing registers into :- 4 verilog register banks (8-bits big-endian, 8/16/32-bits little endian T1 data bus)- 4 verilog register banks (8-bits big-endian, 8/16/32-bits little endian T1 data bus)- 2 Verilog header file containing respectively registers offsets and registers values- 2 Corresponding C header fileOPTIONSThe following option is supported for mif2verilog :-out <XML-FileName>.xmlDefine the name of the XML file which will contain the Spirit description of the register bank.(Default : filename.xml)-log <log-fileName>.logDefine the name of the log file generated by the .MIF parser(Default : display on screen)-interFull script becomes interactive (user prompt) and step-by-step process.(Default : not interactive)-versionDisplays the version of each internal tool (ds2spirit, spirit2verilog, ...)
Imaging DivisionImaging DivisionST MicroelectronicsST MicroelectronicsOPTIONS-i <filename> Specify the input XML file with complete path(Mandatory)-o <directory> Specify the destination directory to write RTL(Optional : Default is ./vrad_verif)-c <integer> Specify the coverage option (Optional: 0 for NOand 1 for YES, Default: 1)-h To get access to help-v To know tool versionspirit2vrad - used to convert a xml filespirit2vrad - used to convert a xml fileinto e filesinto e files
Imaging DivisionImaging DivisionST MicroelectronicsST MicroelectronicsRegister VerificationRegister VerificationStandard ‘vr_ad’ eVC is used in conjuction with register interfaceeVC(Everest) for efficient register verification.Whenever the IP registers are read/written, the associated ‘vr_ad’ eVCpre-defined registers are also updated and IP register contents will beverified by a self-checking scheme.
Imaging DivisionImaging DivisionST MicroelectronicsST MicroelectronicsRegisters in the Register InterfaceRegisters in the Register InterfaceeVC(Everest ) ArchitectureeVC(Everest ) ArchitectureRegister InterfaceeVC(Everest) EnvAddress mapMasterAgent SequenceDriverMonitor BFMImage Signal Processing IP moduleReg.Seq.Driverreg_file
Imaging DivisionImaging DivisionST MicroelectronicsST MicroelectronicsImage Processing Algorithm Bit AccurateImage Processing Algorithm Bit AccurateVerificationVerificationFor the purpose of output video data checking, ’C’/Nathair model isintegrated with the generic verification environment.Output of ‘C’/Nathair model is compared with the output of the IP indata checkersSeparate data checkers are used for the register interfaceeVC(Everest) and video data interface eVC(IDP/VDB/RG/ISB).Data checkers of register and video data interface eVC’s areautomatically generated by IP-XACT API clients.
Imaging DivisionImaging DivisionST MicroelectronicsST MicroelectronicsData Checker and ‘C’/Nathair ModelData Checker and ‘C’/Nathair ModelTestcase for imagedataControlDataRegister interfaceeVC(Everest)Video Data interfaceeVCImage SignalProcessing IP (RTL)C/Nathair ModelIP Output(Status or/and data)C/Nathair Model Output(Status or/and data (image))Data CheckerImage GeneratorTestcase for registersdatavr_ad register model(generator)MemoryModel
Imaging DivisionImaging DivisionST MicroelectronicsST MicroelectronicsUsage of Verification Environment atUsage of Verification Environment atSub-System LevelSub-System LevelAll the R IP’s in Image signal processor pipe are connected serially.Thus, Either ‘C’ models of the image signal processing IP’s areconnected serially in the same order as the corresponding Imagesignal processing IP’s or Single Nathair(Python) model of Imagesignal processor pipe is developed.Input image Data will be driven to the first image signal processingIP and ‘C’/Nathair Model and Output data of Rth image signalprocessing IP and ‘C’/Nathair model will be compared.R register files (of vr_ad register model) are required for R IP’s. Rregister files can be added to the address map (by setting theabsolute base address for each register file). This can be done atruntime or at post-generate.
Imaging DivisionImaging DivisionST MicroelectronicsST MicroelectronicsEnvironment for Verification ofEnvironment for Verification ofImage signal processor pipeImage signal processor pipe(Sub-System Level)(Sub-System Level)ScoreboardNathair(Python) model of Image signal processor pipeImage signalprocessing IP1Video DataInterface eVCoutput BFMImage signalprocessing IP2Image signalprocessing IPrVideo DataInterface eVCinput BFMRegister Interface eVCvr_ad register model with reg filesfor IP1, IP2 …, IPr
Imaging DivisionImaging DivisionST MicroelectronicsST MicroelectronicsApr 22, 201324Verification CockpitVerification CockpitIt isA Linux compatible product installed & already used on several ST sites bylots of usersAn infrastructure tool that bridges other tools such as Specman, NCSim,eManager, CertitudeA tool that integrates with LSF & ClearcaseHighly customizable to fit your needsA tool that will enhance your productivityIt is notA Cadence toolA replacement of Specman, Enterprise Manager or Certitude
Imaging DivisionImaging DivisionST MicroelectronicsST MicroelectronicsApr 22, 201325vManager using Verification CockpitvManager using Verification CockpitFor running regressions and coverage analysis, vManager tool isused.Verification Cockpit is helpful for simple setup of vManagerAutomatic generation of VSIF file from CSV file.Option for launching regressions from web server.Central maintenanceBenefits of best practices and avoid common mistakes.