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Instruction Set Architecture (ISA)

Gaditek
Gaditek

Instruction Set Architecture (ISA)

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+
Computer Architecture
CNE-301
Lecturer: Irfan Ali
+ Instruction Set Architecture (ISA)
• Serves as an interface between software and
hardware.
• Provides a mechanism by which the software tells
the hardware what should be done.
instruction set
High level language code : C, C++, Java, Fortran,
hardware
Assembly language code: architecture specific statements
Machine language code: architecture specific bit patterns
software
compiler
assembler
+ Instruction Set Design Issues
Instruction set design issues include:
 Where are operands stored?
 registers, memory, stack, accumulator
 How many explicit operands are there?
 0, 1, 2, or 3
 How is the operand location specified?
 register, immediate, indirect, . . .
 What type & size of operands are supported?
 byte, int, float, double, string, vector. . .
 What operations are supported?
 add, sub, mul, move, compare . . .
+ Classifying ISAs
Accumulator (before 1960):
1-address add A acc ¬ acc +
mem[A]
Stack (1960s to 1970s):
0-address add tos ¬ tos + next
Memory-Memory (1970s to 1980s):
2-address add A, B mem[A] ¬
mem[A] + mem[B]
3-address add A, B, C mem[A] ¬
mem[B] + mem[C]
+
Register-Memory (1970s to present, e.g. 80x86):
2-address add R1, A R1 ¬ R1 + mem[A]
load R1, A R1 ¬ mem[A]
Register-Register (Load/Store) (1960s to present, e.g. MIPS):
3-address add R1, R2, R3 R1 ¬ R2 + R3
load R1, R2 R1 ¬ mem[R2]
store R1, R2 mem[R1] ¬ R2
+ Operand Locations in Four ISA
Classes GPR

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Instruction Set Architecture (ISA)

  • 2. + Instruction Set Architecture (ISA) • Serves as an interface between software and hardware. • Provides a mechanism by which the software tells the hardware what should be done. instruction set High level language code : C, C++, Java, Fortran, hardware Assembly language code: architecture specific statements Machine language code: architecture specific bit patterns software compiler assembler
  • 3. + Instruction Set Design Issues Instruction set design issues include:  Where are operands stored?  registers, memory, stack, accumulator  How many explicit operands are there?  0, 1, 2, or 3  How is the operand location specified?  register, immediate, indirect, . . .  What type & size of operands are supported?  byte, int, float, double, string, vector. . .  What operations are supported?  add, sub, mul, move, compare . . .
  • 4. + Classifying ISAs Accumulator (before 1960): 1-address add A acc ¬ acc + mem[A] Stack (1960s to 1970s): 0-address add tos ¬ tos + next Memory-Memory (1970s to 1980s): 2-address add A, B mem[A] ¬ mem[A] + mem[B] 3-address add A, B, C mem[A] ¬ mem[B] + mem[C]
  • 5. + Register-Memory (1970s to present, e.g. 80x86): 2-address add R1, A R1 ¬ R1 + mem[A] load R1, A R1 ¬ mem[A] Register-Register (Load/Store) (1960s to present, e.g. MIPS): 3-address add R1, R2, R3 R1 ¬ R2 + R3 load R1, R2 R1 ¬ mem[R2] store R1, R2 mem[R1] ¬ R2
  • 6. + Operand Locations in Four ISA Classes GPR
  • 7. + Code Sequence C = A + B for Four Instruction Sets Stack Accumulator Register (register-memory) Register (load-store) Push A Push B Add Pop C Load A Add B Store C Load R1, A Add R1, B Store C, R1 Load R1,A Load R2, B Add R3, R1, R2 Store C, R3 memory memory acc = acc + mem[C] R1 = R1 + mem[C] R3 = R1 + R2
  • 8. + More About General Purpose Registers  Why do almost all new architectures use GPRs?  Registers are much faster than memory (even cache)  Register values are available immediately  When memory isn’t ready, processor must wait (“stall”)  Registers are convenient for variable storage  Compiler assigns some variables just to registers  More compact code since small fields specify registers (compared to memory addresses) Registers Cache MemoryProcessor Disk
  • 9. + Stack Architectures  Instruction set: add, sub, mult, div, . . . push A, pop A  Example: A*B - (A+C*B) push A push B mul push A push C push B mul add sub A B A A*B A*B A*B A*B A A C A*B A A*B A C B B*C A+B*C result
  • 10. + Stacks: Pros and Cons – Pros – Good code density (implicit top of stack) – Low hardware requirements – Easy to write a simpler compiler for stack architectures – Cons – Stack becomes the bottleneck – Little ability for parallelism or pipelining – Data is not always at the top of stack when need, so additional instructions like TOP and SWAP are needed – Difficult to write an optimizing compiler for stack architectures
  • 11. Accumulator Architectures  Instruction set: add A, sub A, mult A, div A, . . . load A, store A  Example: A*B - (A+C*B)  load B  mul C  add A  store D  load A  mul B  sub D B B*C A+B*C AA+B*C A*B result acc = acc +,-,*,/ mem[A]
  • 12. Accumulators: Pros and Cons ● Pros  Very low hardware requirements  Easy to design and understand ● Cons  Accumulator becomes the bottleneck  Little ability for parallelism or pipelining  High memory traffic
  • 13. Memory-Memory Architectures • Instruction set: (3 operands) add A, B, C sub A, B, C mul A, B, C (2 operands) add A, B sub A, B mul A, B • Example: A*B - (A+C*B) – 3 operands 2 operands – mul D, A, B mov D, A – mul E, C, B mul D, B – add E, A, E mov E, C – sub E, D, E mul E, B – add E, A – sub E, D
  • 14. Memory-Memory:Pros and Cons • Pros – Requires fewer instructions (especially if 3 operands) – Easy to write compilers for (especially if 3 operands) • Cons – Very high memory traffic (especially if 3 operands) – Variable number of clocks per instruction – With two operands, more data movements are required
  • 15. Register-Memory Architectures • Instruction set: add R1, A sub R1, A mul R1, B load R1, A store R1, A • Example: A*B - (A+C*B) load R1, A mul R1, B /* A*B */ store R1, D load R2, C mul R2, B /* C*B */ add R2, A /* A + CB */ sub R2, D /* AB - (A + C*B) */ R1 = R1 +,-,*,/ mem[B]
  • 16. Memory-Register: Pros and Cons ● Pros ● Some data can be accessed without loading first ● Instruction format easy to encode ● Good code density ● Cons ● Operands are not equivalent ● Variable number of clocks per instruction ● May limit number of registers
  • 17. Load-Store Architectures • Instruction set: add R1, R2, R3 sub R1, R2, R3 mul R1, R2, R3 load R1, &A store R1, &A move R1, R2 • Example: A*B - (A+C*B) load R1, &A load R2, &B load R3, &C mul R7, R3, R2 /* C*B */ add R8, R7, R1 /* A + C*B */ mul R9, R1, R2 /* A*B */ sub R10, R9, R8 /* A*B - (A+C*B) */ R3 = R1 +,-,*,/ R2
  • 18. Load-Store: Pros and Cons Pros ● Simple, fixed length instruction encodings ● Instructions take similar number of cycles ● Relatively easy to pipeline and make superscalar Cons ● Higher instruction count ● Not all instructions need three operands ● Dependent on good compiler
  • 19. + Classification of instructions 4-address instructions 3-address instructions 2-address instructions 1-address instructions 0-address instructions
  • 20. + Classification of instructions (continued…) The 4-address instruction specifies the two source operands, the destination operand and the address of the next instruction op code source 2destination next addresssource 1
  • 21. + Classification of instructions (continued…) A 3-address instruction specifies addresses for both operands as well as the result op code source 2destination source 1
  • 22. +Classification of instructions (continued…) A 2-address instruction overwrites one operand with the result One field serves two purposes op code destination source 1 source 2 • A 1-address instruction has a dedicated CPU register, called the accumulator, to hold one operand & the result –No address is needed to specify the accumulator op code source 2
  • 23. + Classification of instructions (continued…) A 0-address instruction uses a stack to hold both operands and the result. Operations are performed between the value on the top of the stack TOS) and the second value on the stack (SOS) and the result is stored on the TOS op code
  • 24. + Comparison of instruction formats As an example assume: that a single byte is used for the op code the size of the memory address space is 16 Mbytes a single addressable memory unit is a byte Size of operands is 24 bits Data bus size is 8 bits
  • 25. + Comparison of instruction formats We will use the following two parameters to compare the five instruction formats mentioned before Code size  Has an effect on the storage requirements Number of memory accesses  Has an effect on execution time
  • 26. + 4-address instruction Code size = 1+3+3+3+3 = 13 bytes No of bytes accessed from memory 13 bytes for instruction fetch + 6 bytes for source operand fetch + 3 bytes for storing destination operand Total = 22 bytes op code source 2destination next addresssource 1 1 byte 3 bytes 3 bytes 3 bytes3 bytes
  • 27. + 3-address instruction Code size = 1+3+3+3 = 10 bytes No of bytes accessed from memory 10 bytes for instruction fetch + 6 bytes for source operand fetch + 3 bytes for storing destination operand Total = 19 bytes 1 byte 3 bytes 3 bytes3 bytes op code source 2destination source 1
  • 28. + 2-address instruction Code size = 1+3+3 = 7 bytes No of bytes accessed from memory 7 bytes for instruction fetch + 6 bytes for source operand fetch + 3 bytes for storing destination operand Total = 16 bytes op code destination source 1 source 2 1 byte 3 bytes3 bytes
  • 29. + 1-address instruction Code size = 1+3= 4 bytes No of bytes accessed from memory 4 bytes for instruction fetch + 3 bytes for source operand fetch + 0 bytes for storing destination operand Total = 7 bytes 1 byte 3 bytes op code source 2
  • 30. + 0-address instruction Code size = 1= 1 bytes # of bytes accessed from memory 1 bytes for instruction fetch + 6 bytes for source operand fetch + 3 bytes for storing destination operand Total = 10 bytes 1 byte op code
  • 31. + Summary Instruction Format Code size Number of memory bytes 4-address instruction 13 22 3-address instruction 10 19 2-address instruction 7 16 1-address instruction 4 7 0-address instruction 1 10
  • 32. + Example 2.1 text expression evaluation a = (b+c)*d - e 3-Address 2-Address 1-Address 0-Address add a, b, c mpy a, a, d sub a, a, e load a, b add a, c mpy a, d sub a, e lda b add c mpy d sub e sta a push b push c add push d mpy push e sub pop a
  • 33. + Immediate Addressing Mode  Data for the instruction is part of the instruction itself  No need to calculate any address  Limited range of operands:
  • 34. + Immediate addressing mode Example: lda 123 123Op code Memory No memory access needed IR 123ACC data : : : :
  • 35. + Direct Addressing mode Example: lda [123] *** 123 Opcode 123 456 456 Memory . . . data address IR ACC
  • 36. + Indirect addressing mode Example: lda [[123]] 456 : 789 Memory Opcode 123 789 Address of pointer Address of data data 123 456 IR ACC
  • 37. + Register (direct) addressing mode (continued…) Example: lda R2 Op code address of R2 1234 1234 Address of data data IR R1 R2 R3 R4 ACC Memory : : : : No memory access needed
  • 38. +Register Indirect Addressing Example: lda [R1] 456 Op code Address of R1 456 Memory IR R1 R2 R3 R4 123 register contains memory address CPU Registers data e instruction points to a CPU register 123 ACC
  • 39. MemoryExample: lda [ R1 + 8 ] 8IR Op code Address of R1 Register address R 1 R 2 120 + Memory address Index 456 128 CPU registers ACC 456 data Displacement Addressing constant
  • 40. +Relative Addressing Example: jump 4 Opcode 4 Memory IR 12 0 + Address of the next instruction PC 124Next instruction …...
  • 41. + RISC Stands for Reduced Instruction Set Computers A concept or philosophy of machine design; not a set of architectural features Underlying idea is to reduce the number and complexity of instructions New RISC computers may have some instruction that are quite complex
  • 42. + Features of RISC machines One instruction per clock period All instructions have the same size CPU accesses memory only for Load and Store operations Simple and few addressing modes
  • 44. + Features of CISC machines More work per instruction Wide variety of addressing modes Variable instruction lengths and execution times per instruction CISC machines attempt to reduce the “semantic gap”
  • 45. + Disadvantages of CISC Clock period,T, cannot be reduced beyond a certain limit Complex addressing modes delay operand fetch from memory Difficult to make efficient use of speedup techniques

Editor's Notes

  1. <number>
  2. An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O. An ISA includes a specification of the set of opcodes (machine language), and the native commands implemented by a particular processor
  3. Microprocessor without Interlocked Pipeline Stages
  4. A stack is a group of registers organized as a last-in-first-out (LIFO) structure. In such a structure, the operands stored first, through the push operation, can only be accessed last, through a pop operation; the order of access to the operands is reverse of the storage operation. An analogy of the stack is a “plate-dispenser” found in several self-service cafeterias. Arithmetic and logic operations successively pick operands from the top-ofthe-stack (TOS), and push the results on the TOS at the end of the operation. In stack based machines, operand addresses need not be specified during the arithmetic or logical operations. Therefore, these machines are also called 0-address machines
  5. Accumulator based machines use special registers called the accumulators to hold one source operand and also the result of the arithmetic or logic operations performed. Thus the accumulator registers collect (or „accumulate‟) data. Since the accumulator holds one of the operands, one more register may be required to hold the address of another operand. The accumulator is not used to hold an address. So accumulator based machines are also called 1-address machines. Accumulator machines employ a very small number of accumulator registers, generally only one. These machines were useful at the time when memory was quite expensive; as they used one register to hold the source operand as well as the result of the operation. However, now that the memory is relatively inexpensive, these are not considered very useful, a
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  7. <number> 4-address instructions are not very common because the next instruction to be executed is sequentially stored next to the current instruction in the memory. Therefore, specifying its address is redundant. Used in encoding microinstructions in a micro-coded control unit (to be studied later)
  8. <number> The address of the next instruction is in the PC
  9. <number> As you can see, the size of the instruction reduces when the addresses reduce. The length of each field will be much smaller for CPU registers as compared to memory locations because there are a lot more memory locations compared to CPU registers
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  11. <number> A single byte, or an 8-bit, op code can be used to encode up to 256 instructions. A 16-Mbyte memory address space will require 24-bit memory addresses. We will assume a byte wide memory organization to make this example different from the example in the book. The size of the address bus will be 24 bits and the size of the data bus will be 8-bits.
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  13. <number> There is no need to fetch the operand corresponding to the next instruction since it has been brought into the CPU during instruction fetch.
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