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Presented by
Rishi Ram khanal
Bim 3rd (TU)
Roll.no:108
 Introduction
 Bus organization
 Table: Encoding of Register selection fields
 Table: Encoding of ALU operation
 Examples of Micro-operation for the CPU
 Symbol Designation
 The number of registers in a processor unit
may vary from just one processor register to
as many as 64 registers or more.
 One of the CPU registers is called as an
accumulator AC or 'A' register. It is the main
operand register of the ALU.
 he instruction register (IR) holds the opcode
of the current instruction.
 The address register (AR) holds the address
of the memory in which the operand resides.
- See more at
 The program counter (PC) holds the address
of the next instruction to be fetched for
execution.
Binary code SEL A SEL B SEL D
000 Input Input None
001 R1
010 R2
011 R3 S S
100 R4 A A
101 R5 M M
110 R6 E E
11 R7
OPR and select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 Add A + B ADD
00101 Subtract A-B SUB
00110 Decrement A DEC A
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA
Micro
Opera
tion
SECA SEC B SEL D OPR Contr
ol
WOR
D
R1 ®
R2 –
R3
R2 R3 R1 SuB 011 011 001 00101
R4 ®
R5 V
R5
R4 R R OR 100 101 100 0101
R6 ®
R6 + 1
R6 - R MCA 110 000 110 00001
R7 ®
R1
R1 - R TSFA 001 000 111 00000
Outpu
t ®
R2
R2 - None TSFa 010 000 000 00000
General register organization  (computer organization)

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General register organization (computer organization)

  • 1. Presented by Rishi Ram khanal Bim 3rd (TU) Roll.no:108
  • 2.  Introduction  Bus organization  Table: Encoding of Register selection fields  Table: Encoding of ALU operation  Examples of Micro-operation for the CPU  Symbol Designation
  • 3.  The number of registers in a processor unit may vary from just one processor register to as many as 64 registers or more.  One of the CPU registers is called as an accumulator AC or 'A' register. It is the main operand register of the ALU.  he instruction register (IR) holds the opcode of the current instruction.
  • 4.  The address register (AR) holds the address of the memory in which the operand resides. - See more at  The program counter (PC) holds the address of the next instruction to be fetched for execution.
  • 5.
  • 6. Binary code SEL A SEL B SEL D 000 Input Input None 001 R1 010 R2 011 R3 S S 100 R4 A A 101 R5 M M 110 R6 E E 11 R7
  • 7. OPR and select Operation Symbol 00000 Transfer A TSFA 00001 Increment A INCA 00010 Add A + B ADD 00101 Subtract A-B SUB 00110 Decrement A DEC A 01000 AND A and B AND 01010 OR A and B OR 01100 XOR A and B XOR 01110 Complement A COMA 10000 Shift right A SHRA 11000 Shift left A SHLA
  • 8. Micro Opera tion SECA SEC B SEL D OPR Contr ol WOR D R1 ® R2 – R3 R2 R3 R1 SuB 011 011 001 00101 R4 ® R5 V R5 R4 R R OR 100 101 100 0101 R6 ® R6 + 1 R6 - R MCA 110 000 110 00001 R7 ® R1 R1 - R TSFA 001 000 111 00000 Outpu t ® R2 R2 - None TSFa 010 000 000 00000