Computer organization - Instructions Set

1. +
Computer Architecture
CNE-301
Lecturer: Irfan Ali

2. + Instruction Set Architecture (ISA)
• Serves as an interface between software and
hardware.
• Provides a mechanism by which the software tells
the hardware what should be done.
High level language code : C, C++, Java, Fortran,
compiler
Assembly language code: architecture specific statements
assembler
Machine language code: architecture specific bit patterns
software
instruction set
hardware

3. + Instruction Set Design Issues
■Instruction set design issues include:
■ Where are operands stored?
■ registers, memory, stack, accumulator
■ How many explicit operands are there?
■ 0, 1, 2, or 3
■ How is the operand location specified?
■ register, immediate, indirect, . . .
■ What type & size of operands are supported?
■ byte, int, float, double, string, vector. . .
■ What operations are supported?
■ add, sub, mul, move, compare . . .

4. + Classifying ISAs
add A acc  acc +
Accumulator (before 1960):
1-address
mem[A]
Stack (1960s to 1970s):
0-address add tos  tos + next
Memory-Memory (1970s to 1980s):
add A, B mem[A] 
add A, B, C mem[A] 
2 address
mem[A] + mem[B]
3 address
mem[B] + mem[C]

5. +
Register-Memory (1970s to present, e.g. 80x86):
2-address add R1, A R1 
load R1, A R1 
R1 + mem[A]
mem[A]
Register-Register (Load/Store) (1960s to present, e.g. MIPS):
3-address add R1, R2, R3 R1  R2 + R3
load R1, R2 R1  mem[R2]
store R1, R2 mem[R1]  R2

6. + Operand Locations in Four ISA
C lasses GPR

7. + Code Sequence C = A + B
for Four Instruction Sets
Stack Accumulator Register
(load-store)
Push A
Push B
Add
Pop C
Load A
Add B
Store C
Register
(register-memory)
Load R1, A
Add R1, B
Store C, R1
Load R1,A
Load R2, B
Add R3, R1, R2
Store C, R3
memory
memory
acc = acc + mem[C] R1 = R1 + mem[C] R3 = R1 + R2

8. + More About General Purpose Registers
■ Why do almost all new architectures use GPRs?
■
■
■
■
■
■ Registers are much faster than memory (even cache)
Register values are available immediately
When memory isn’t ready, processor must wait (“stall”)
Registers are convenient for variable storage
Compiler assigns some variables just to registers
More compact code since small fields specify registers
(compared to memory addresses)
Registers Cache
Memory
Processor Disk

9. + Stack Architectures
■ Instruction set:
add, sub, mult, div, . . .
push A, pop A
■Example: A*B - (A+C *B)
push A
push B
mul
push A
push C
push B
mul
add
sub
A B A*B
A A*B
A*B
A
A C
A
A*B
B
C
A
A*B
B*C A+B*C
A*B
result

10. + Stacks: Pros and Cons
– Pros
– Good code density (implicit top of stack)
– Low hardware requirements
– Easy to write a simpler compiler for stack
architectures
– Cons
– Stack becomes the bottleneck
– Little ability for parallelism or pipelining
– Data is not always at the top of stack when need, so
additional instructions like TOP and SWAP are needed
– Difficult to write an optimizing compiler for stack
architectures

11. Accumulator Architectures
■ Instruction set:
add A, sub A, mult A, div A, . . .
load A, store A
■ Example: A*B - (A+C *B)
■ load B
■ mul C
■ add A
■ store D
■ load A
■ mul B
■ sub D
B B*C A+B*C A
A+B*C A*B result
acc = acc +,-,*,/ mem[A]

12. Accumulators: Pros and Cons
●
Pros
■ Very low hardware requirements
■ Easy to design and understand
●
C ons
■ Accumulator becomes the bottleneck
■ Little ability for parallelism or
pipelining
■ High memory traffic

13. Memory-Memory Architectures
add A, B, C sub A, B, C mul A, B, C
• Instruction set:
(3 operands)
(2 operands) add A, B sub A, B mul A, B
• Example: A*B - (A+C*B)
– 3 operands
– mul D, A, B
– mul E, C, B
– add E, A, E
– sub E, D, E
–
–
2 operands
mov D, A
mul D, B
mov E, C
mul E, B
add E, A
sub E, D

14. Memory-Memory:Pros and
Cons
• Pros
– Requires fewer instructions (especially if 3 operands)
– Easy to write compilers for (especially if 3 operands)
• Cons
– Very high memory traffic (especially if 3 operands)
– Variable number of clocks per instruction
– With two operands, more data movements are required

15. Register-Memory Architectures
• Instruction set:
add R1, A sub R1, A mul R1, B
load R1, A store R1, A
• Example: A*B - (A+C*B)
load R1, A
mul R1, B /* A*B */
store R1, D
load R2, C
mul R2, B /* C*B */
add R2, A /* A + CB */
sub R2, D /* AB - (A + C*B) */
R1 = R1 +,-,*,/ mem[B]

16. Memory-Register: Pros and Cons
● Pros
● Some data can be accessed without loading first
● Instruction format easy to encode
● Good code density
● Cons
● Operands are not equivalent
● Variable number of clocks per instruction
● May limit number of registers

17. Load-Store Architectures
• Instruction set:
add R1, R2, R3 sub R1, R2, R3 mul R1, R2, R3
load R1, &A store R1, &A move R1, R2
• Example: A*B - (A+C *B)
load R1, &A
load R2, &B
load R3, &C
/* C *B */
/* A + C *B */
/* A*B */
mul R7, R3, R2
add R8, R7, R1
mul R9, R1, R2
sub R10, R9, R8 /* A*B - (A+C *B) */
R3 = R1 +,-,*,/ R2

18. ■Load-Store: Pros and Cons
Pros
●
●
●
Simple, fixed length instruction encodings
Instructions take similar number of cycles
Relatively easy to pipeline and make superscalar
C ons
●
●
●
Higher instruction count
Not all instructions need three operands
Dependent on good compiler

19. +
Classification of instructions
■4-address instructions
■3-address instructions
■2-address instructions
■1-address instructions
■0-address instructions

20. +
Classification of instructions
(continued…)
■The 4-address instruction specifies the two
source operands, the destination operand and
the address of the next instruction
op code destination source 1 source 2 next address

21. +
Classification of instructions
(continued…)
■A 3-address instruction specifies addresses for
both operands as well as the result
op code destination source 1 source 2

22. +Classification of instructions
(continued…)
■A 2-address instruction overwrites one operand
with the result
■One field serves two purposes
op code destination
source 1
source 2
• A1-address instruction has a dedicated CPU register,
called the accumulator, to hold one operand & the
result –No address is needed to specify the
accumulator
op code source 2

23. +
Classification of instructions
(continued…)
■A 0-address instruction uses a stack to hold
both operands and the result. Operations are
performed between the value on the top of the
stack TOS) and the second value on the stack
(SOS) and the result is stored on the TOS
op code

24. +
Comparison of
instruction formats
As an example assume:
■that a single byte is used for the op code
■the size of the memory address space is 16
Mbytes
■a single addressable memory unit is a byte
■Size of operands is 24 bits
■Data bus size is 8 bits

25. +
Comparison of
instruction formats
■We will use the following two
parameters to compare the five
instruction formats mentioned before
■Code size
■ Has an effect on the storage requirements
■Number of memory accesses
■ Has an effect on execution time

26. +
4-address instruction
■Code size = 1+3+3+3+3 = 13 bytes
■ No of bytes accessed from memory
13 bytes for instruction fetch +
6 bytes for source operand fetch +
3 bytes for storing destination operand
Total = 22 bytes
op code destination source 1 source 2 next address
1 byte 3 bytes 3 bytes 3 bytes 3 bytes

27. +
3-address instruction
■Code size = 1+3+3+3 = 10 bytes
■ No of bytes accessed from memory
10 bytes for instruction fetch +
6 bytes for source operand fetch +
3 bytes for storing destination operand
Total = 19 bytes
1 byte 3 bytes 3 bytes 3 bytes
op code destination source 1 source 2

28. +
2-address instruction
■Code size = 1+3+3 = 7 bytes
■ No of bytes accessed from memory
7 bytes for instruction fetch +
6 bytes for source operand fetch +
3 bytes for storing destination operand
Total = 16 bytes
op code destination
source 1
source 2
1 byte 3 bytes 3 bytes

29. +
1-address instruction
■Code size = 1+3= 4 bytes
■ No of bytes accessed from memory
4 bytes for instruction fetch +
3 bytes for source operand fetch +
0 bytes for storing destination operand
Total = 7 bytes
1 byte 3 bytes
op code source 2

30. +
0-address instruction
■Code size = 1= 1 bytes
■ # of bytes accessed from memory
1 bytes for instruction fetch +
6 bytes for source operand fetch +
3 bytes for storing destination operand
Total = 10 bytes
1 byte
op code

31. +
Summary
Instruction Format Code
size
Number of
memory bytes
4-address instruction 13 22
3-address instruction 10 19
2-address instruction 7 16
1-address instruction 4 7
0-address instruction 1 10

32. +
Example 2.1 text
expression evaluation a = (b+c)*d
- e
3-Address 2-Address 1-Address 0-Address
add a, b, c load a, b lda b push b
mpy a, a, d add a, c add c push c
sub a, a, e mpy a, d mpy d add
sub a, e sub e push d
sta a mpy
push e
sub
pop a

33. +
Immediate Addressing
Mode
■ Data for the instruction is part of the instruction itself
■ No need to calculate any address
■ Limited range of operands:

34. +
Immediate addressing
mode
Example: lda 123
123
Op code
No memory access needed
IR
123
ACC
data
:
:
:
Memory :

35. +
Direct Addressing mode
Example: lda [123] ***
123
Opcode 123
456
456
Memory
.
.
.
data
address
IR
ACC

36. +
Indirect addressing mode
Example: lda [[123]]
456
:
789
Memory
pcode 123
789
Address of pointer
data
123
Address of data
456
IRO
ACC

37. +
Register (direct) addressing
mode (continued…)
Example: lda R2
Op code address of R2
1234
1234
Address of data
data
IR
R1
R2
R3
R4
ACC :
:
:
Memory :
No memory access needed

38. +Register Indirect Addressing
Example: lda [R1]
456
Op code Address of R1
456
Memory
IR
R1
R2
R3
R4
123
register
contains
memory
address
CPU Registers
data
instruction points to a CPU register
123
ACC

39. Memory
Example: lda [ R1 + 8 ]
8
IR Op code Address of R1
+ Memory
address
Index
120
456 128
R 1
R 2
CPU registers
ACC 456
data
Displacement Addressing
constant

40. +Relative Addressing
Example: jump 4
Opcode 4
Memory
IR
12
0
+
Address of the
next instruction
PC
Next instruction124
…...

41. +
RISC
■Stands for Reduced Instruction Set Computers
■A concept or philosophy of machine design; not
a set of architectural features
■Underlying idea is to reduce the number and
complexity of instructions
■New RISC computers may have some
instruction that are quite complex

42. +
Features of RISC machines
■One instruction per clock period
■All instructions have the same size
■CPU accesses memory only for Load and Store
operations
■Simple and few addressing modes

43. +
C ISC
Complex Instruction Set Computers

44. +
Features of C ISC machines
■More work per instruction
■Wide variety of addressing modes
■Variable instruction lengths and execution
times per instruction
■CISC machines attempt to reduce the
“semantic gap”

45. +
Disadvantages of C ISC
■C lock period, T
, cannot be reduced beyond
a certain limit
■Complex addressing modes delay operand
fetch from memory
■Difficult to make efficient use of speedup
techniques