Dealing with Exceptions Computer Architecture

1. Lecture 7
Dealing with Exceptions
Computer Architecture
CNE-301
Lecturer: Irfan Ali
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Exception Categories

8. Two Types of Exceptions: Interrupts and Traps
• Interrupts
• Caused by external events:
• Network, Keyboard, Disk I/O, Timer
• Page fault - virtual memory
• System call - user request for OS action
• Asynchronous to program execution
• May be handled between instructions
• Simply suspend and resume user program
• Traps
• Caused by internal events
• Exceptional conditions (overflow)
• Undefined Instruction
• Hardware malfunction
• Usually Synchronous to program execution
• Condition must be remedied by the handler
• Instruction may be retried or simulated and program continued or program may be aborted
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9. Synchronous vs Asynchronous
• Definition: If the event occurs at the same place
every time the program is executed with the same
data and memory allocation, the event is
synchronous. Otherwise asynchronous.
• Except for hardware malfunctions, asynchronous
events are caused by devices external to the CPU
and memory.
• Asynchronous events usually are easier to handled
because asynchronous events can be handled after
the completion of the current instruction.
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10. Exceptions in Simple five-stage
pipeline
• Instruction Fetch, & Memory stages
• Page fault on instruction/data fetch
• Misaligned memory access
• Memory-protection violation
• Instruction Decode stage
• Undefined/illegal opcode
• Execution stage
• Arithmetic exception
• Write-Back stage
• No exceptions!
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11. What happens during an exception
In The Hardware
• The pipeline has to
1) stop executing the offending instruction in midstream,
2) let all preceding instructions complete,
3) flush all succeeding instructions,
4) set a register to show the cause of the exception,
5) save the address of the offending instruction, and
6) then jump to a prearranged address (the address of the exception handler code)
In The Software
• The software (OS) looks at the cause of the exception and “deals” with it
• Normally OS kills the program
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12. Exceptions
Exception = non-programmed control transfer
• system takes action to handle the exception
• must record the address of the offending instruction
• record any other information necessary to return afterwards
• returns control to user
• must save & restore user state
user program
normal control flow:
sequential, jumps, branches, calls, returns
System
Exception
Handler
Exception:
return from
exception
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must record

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What Makes Pipelining
Hard?
Examples of interrupts:
• Power failing,
• Arithmetic overflow,
• I/O device request,
• OS call,
• Page fault
Interrupts (also known as: faults, exceptions,
traps) often require
• surprise jump (to vectored address)
• linking return address
• saving of PSW-Program Status Word (including CCs-
Condition Codes)
• state change (e.g., to kernel mode)
Interrupts cause
great havoc!
There are 5 instructions executing
in 5 stage pipeline when an
interrupt occurs:
• How to stop the pipeline?
• How to restart the pipeline?
• Who caused the interrupt?

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What Makes Pipelining
Hard?
Interrupts cause
great havoc!
What happens on interrupt while in delay slot ?
• Next instruction is not sequential
solution #1: save multiple PCs
• Save current and next PC
• Special return sequence, more complex hardware
solution #2: single PC plus
• Branch delay bit
• PC points to branch instruction
Stage Problem that causes the interrupt
IF Page fault on instruction fetch; misaligned memory
access; memory-protection violation
ID Undefined or illegal opcode
EX Arithmetic interrupt
MEM Page fault on data fetch; misaligned memory
access; memory-protection violation

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What Makes
Pipelining Hard?
• Simultaneous exceptions in more than one pipeline stage, e.g.,
• Load with data page fault in MEM stage
• Add with instruction page fault in IF stage
• Add fault will happen BEFORE load fault
• Solution #1
• Interrupt status vector per instruction
• Defer check until last stage, kill state update if exception
• Solution #2
• Interrupt ASAP(as soon as possible)
• Restart everything that is incomplete
Another advantage for state update late in pipeline!
Interrupts cause
great havoc!

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What Makes
Pipelining Hard?
Here’s what happens on a data page fault.
1 2 3 4 5 6 7 8 9
i F D X M W
i+1 F D X M W < page fault
i+2 F D X M W < squash
i+3 F D X M W < squash
i+4 F D X M W < squash
i+5 trap > F D X M W
i+6 trap handler > F D X M W
Interrupts cause
great havoc!

21. Exceptions - “Stuff Happens”
• Exceptions definition: “unexpected change in
control flow”
• Another form of control hazard.
For example:
add $1, $2, $1; causing an arithmetic overflow
sw $3, 400($1);
add $5, $1, $2;
Invalid $1 contaminates other registers or memory locations!
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22. Additions to MIPS ISA to support Exceptions
• EPC (Exceptional Program Counter)
• A 32-bit register
• Hold the address of the offending instruction
• Cause
• A 32-bit register in MIPS (some bits are unused currently.)
• Record the cause of the exception
• Status - interrupt mask and enable bits and determines what exceptions can occur.
• Control signals to write EPC , Cause, and Status
• Be able to write exception address into PC, increase mux set PC to exception address (MIPS uses 8000
00180hex ).
• May have to undo PC = PC + 4, since want EPC to point to offending instruction (not its successor); PC =
PC – 4
• What else?
flush all succeeding instructions in pipeline
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23. Flush instructions in Branch Hazard
36 sub $10, $4, $8
40 beq $1, $3, 7 # taget = 40 + 4 + 7*4 = 72
44 and $12, $2, $5 if($1==$2)
48 or $13, $2, $6 go(PC+4+PC*C)
52 ….
….
72 lw $4, 50($7)
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25. Pipelining in MIPS
• MIPS architecture was designed to be pipelined
• Simple instruction format (makes IF, ID easy)
• Single-word instructions
• Small number of instruction formats
• Common fields in same place (e.g., rs, rt) in different formats
• Memory operations only in lw, sw instructions
(simplifies EX)
• Memory operands aligned in memory (simplifies MEM)
• Single value for Write-Back (limits forwarding)
• Pipelining is harder in CISC architectures
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Key observation: architected state only change in memory and
register write stages.

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30. Introduction to ILP
• What is ILP?
• Processor and Compiler design techniques that speed up execution by causing
individual machine operations to execute in parallel
• ILP is transparent to the user
• Multiple operations executed in parallel even though the system is handed a
single program written with a sequential processor in mind
• Same execution hardware as a normal RISC machine
• May be more than one of any given type of hardware

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This allows us to replace the loop above with the following code sequence, which makes
possible overlapping of the iterations of the loop:
a[1] = a[1] + b[1];
for (i=1; i<=99; i= i+1){
b[i+1] = c[i] + d[i];
a[i+1] = a[i+1] + b[i+1];
}
b[101] = c[100] + d[100];
Example 3
for (i=1; i<=100; i= i+1){
a[i+1] = a[i] + c[i]; //S1
b[i+1] = b[i] + a[i+1]; //S2
}
This loop is not parallel it has cycles in the dependencies, namely the statements S1 and S2
depend on themselves!

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There are a number of techniques for converting such loop-level
parallelism into instruction-level parallelism. Basically, such
techniques work by unrolling the loop.
An important alternative method for exploiting loop-level
parallelism is the use of vector instructions on a vector
processor.