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Design Basics on Power
Amplifiers
Wednesday, 16th December 2015
Outline
1. Introduction
2. Design
3. Manufacturing
4. Results
5. Conclusions and Future work
What is amplification?
1. Introduction
3
The operation of an electronic device
increasing the power of a signal.
Amplifiers depending on operating frequency
1. Introduction
4
Low frequency High frequency or RF
Transistor
Input Matching
Network
Output Matching
Network
Bias Network
(Gate)
Bias Network
(Drain)
RF in
RF out
Vgs
Vds
1. Introduction
5
Basic Microwave Amplifier scheme
1. Introduction
6
Main concepts to work with:
• Linearity: capability of an amplifier to reproduce
increased exact copies of the input signal.
• Efficiency: how much of the DC power supplied to the
amplifier is transformed into amplification.
They are in inverse proportion.
These characteristics determine the class of the amplifier!
Transistor Characteristic IV Curves
1. Introduction
7
𝑉𝐶𝐸
𝐼 𝐶
𝐼 𝐵 = 100 𝜇𝐴
10 𝑚𝐴
C (Collector)
or D (Drain)
E (Emitter) or
S (Source)
B (Base) or
G (Gate)
20 V
+
_
𝑉𝐶𝐸
𝐼 𝐶
𝑰 𝑩
Load-line
1. Introduction
8
DC equivalent
AC equivalent
𝑉𝐶𝐸
𝐼 𝐶
𝑉𝐶𝐶 − 𝑉𝑅 𝐶
− 𝑉𝐶𝐸 − 𝑉𝑅 𝐸
= 0
𝑉𝐶𝐶 − 𝐼 𝐶 𝑅 𝐶 − 𝑉𝐶𝐸 − 𝐼 𝐸 𝑅 𝐸 = 0
𝑉𝐶𝐶 − 𝐼 𝐶(𝑅 𝐶+𝑅 𝐸) − 𝑉𝐶𝐸 = 0
Load-line equation (y = mx+n):
𝐼 𝐶 = −
1
𝑅 𝐶 + 𝑅 𝐸
𝑉𝐶𝐸 +
𝑉𝐶𝐶
𝑅 𝐶 + 𝑅 𝐸
In saturation… 𝑉𝐶𝐸 ≈ 0Cut-off… 𝐼 𝐶 ≈ 0
𝑉𝐶𝐶
𝑅 𝐶 + 𝑅 𝐸
𝑉𝐶𝐶
Q-Point
Load-line
1. Introduction
9
DC equivalent
AC equivalent
𝑣 𝐶𝐸 = −𝑖 𝐶 𝑟𝐶
𝑉𝐶𝐸 − 𝑉𝐶𝐸𝑄 = − 𝐼 𝐶 − 𝐼 𝐶𝑄 𝑟𝐶
Load-line equation (y = mx+n):
𝐼 𝐶 = −
1
𝑟𝐶
𝑉𝐶𝐸 +
𝑉𝐶𝐸𝑄
𝑟𝐶
+ 𝐼 𝐶𝑄
𝑖 𝐶
𝑉𝐶𝐸
In saturation… 𝑉𝐶𝐸 ≈ 0In Cut-off… 𝐼 𝐶 ≈ 0
Q-Point
𝑰 𝑪𝑸 +
𝑽 𝑪𝑬𝑸
𝒓 𝑪
𝑽 𝑪𝑬𝑸 + 𝑰 𝑪𝑸 𝒓 𝑪
𝐼 𝐶
Load-line
1. Introduction
10
Q-Point
𝑰 𝑪𝑸 +
𝑽 𝑪𝑬𝑸
𝒓 𝑪
𝑽 𝑪𝑬𝑸 + 𝑰 𝑪𝑸 𝒓 𝑪 𝑉𝐶𝐸
𝐼 𝐶
𝑣𝐶𝐸/𝐷𝑆≡𝑣𝑅𝐹𝑜𝑢𝑡
𝑖 𝐶𝐸/𝐷𝑆 ≡ 𝑖 𝑅𝐹𝑜𝑢𝑡
Power Amplifier Classes
1. Introduction
11
Class Conduction Angle
A θ = 2π
AB π < θ < 2π
B θ = π
C θ < π
D – T θ ≈ 0
Power Amplifier Classes
1. Introduction
12
Clase A Clase B
Clase AB Clase C
Power Amplifier Classes
1. Introduction
13
Outline
1. Introduction
2. Design
3. Manufacturing
4. Results
5. Conclusions and Future work
Transistor Tecnology Selection
• GaN HEMT:
 High Efficiency
 High Gain
 Great Bandwidth
 Low Power Consumption
 Selección del Transistor
• CGH40010F (Cree Inc.)
2. Design
15
IV Characteristics and Q-Point
2. Design
16
0 30 60 84
Vds (V)
IV Curves
0
500
1000
1500
2000
2400
Ids(mA)
IV Curves (mA)
Q-Point (28V, 482mA)
𝑽 𝑮𝑺 = −𝟐. 𝟐𝑽
TrVi Ii
S
1 2
3
4 5 6
CGH40010F_R6_VA
ID=Q1
Tbase=25
Rth=8
Swp Step
IVCURVE
ID=IV1
VSWEEP_start=0 V
VSWEEP_stop=84 V
VSWEEP_step=1 V
VSTEP_start=-10 V
VSTEP_stop=2 V
VSTEP_step=0.2 V
• Maximum drain voltage (84 V)
• Maximum drain current (1500 mA)
• Cut-off threshold (67 mA)
• Saturation threshold
• Maximum dissipated power (14 W)
Dynamic/AC Load-line
2. Design
17
TrVi Ii
S
1 2
3
4 5 6
CGH40010F_R6_VA
ID=Q1
Tbase=25
Rth=8
0.000399mA
-2.2V
482mA
28V
482mA
0V
0mA
27.7V
482mA
0V
0mA
107V
I_METER
ID=Id_intr
482mA
V_METER
ID=Vd_intr
DCVS
ID=Vgs
V=-2.2 V
0.000398mA
-2.2V
I_METER
ID=I_in
0mA
0V
0V
I_METER
ID=Ig
0.000399mA
-2.2V
DCVS
ID=Vdc
V=28 V
482mA
28V
V_METER
ID=Vd
I_METER
ID=Id
482mA
28V
3:Bias
12
LTUNER2
ID=TU3
Mag=0
Ang=0 Deg
Zo=50 Ohm
0.000399mA0mA
0.000398mA
3:Bias
1 2
LTUNER2
ID=TU1
Mag=0
Ang=0 Deg
Zo=50 Ohm
482mA 0mA
0V
482mA
V_METER
ID=VM_trise
PORT
P=2
Z=50 Ohm
0mA
PORT_PS1
P=1
Z=50 Ohm
PStart=0.6 dBm
PStop=40.6 dBm
PStep=1 dB
0mA
PORT1
P=1
Z=50 Ohm
Pwr=27.6 dBm
Conn_Vi
27.7V
Conn_Vi
27.7V
Conn_Ii
0V
Conn_Ii
0V
0 30 60 84
Vds (V)
IV Curves
0
500
1000
1500
2000
2400
Ids(mA)
28 V
482.3 mA
Vstep = -2.2 V
IV Curves (mA)
DLL @ 7.6dBm (mA)
DLL @ 17.6dBm (mA)
DLL @ P1dB (mA)
0 0.3 0.6 0.816
Time (ns)
RF in VS. RF out
-600
-400
-200
0
200
400
600
P1dBInputPower
-300
-200
-100
0
100
200
300
20dBmInputPower
RF IN @ 20dBm (mA)
RF OUT @ 20dBm (mA)
RF IN @ P1dB (mA)
RF OUT @ P1dB (mA)
0 V
I_METER
ID=Ig
0.000399 mA
-2.2 V
3:Bias
12
LTUNER2
ID=TU3
Mag=0
Ang=0 Deg
Zo=50 Ohm
0.000399 mA0 mA
Gain, Output Power and PAE
2. Design
18
0.6 10.6 20.6 30.6 40.6
Power (dBm)
Pin VS Pout and Gain
0
10
20
30
40
50
27.6 dBm
10.9 dB
18.52 dBm
11.89 dB
Pout (dBm)
PGain (dB)
PAE (%)
Stability
• Critical factor in order to avoid oscillations (Γ > 1)
• This is due to the negative either input or output resistance
2. Design
19
𝑅𝑒 𝑍 𝑆 + 𝑍𝑖𝑛 < 0 𝑅𝑒 𝑍 𝑜𝑢𝑡 + 𝑍 𝐿 < 0
Transistor
Input Matching
Network
Output
Matching
Network
S in out L
0Z
0Z
𝑍 = 𝑍0
1 + Γ
1 − Γ
Conditional Stability
Stability
• Border which delimits between stable and unstable regions:
 Γ𝑖𝑛 = 𝑆11 +
𝑆12 𝑆21Γ 𝐿
1−𝑆22Γ 𝐿
= 1 Γ𝑜𝑢𝑡 = 𝑆22 +
𝑆12 𝑆21Γ 𝑆
1−𝑆11Γ 𝑆
= 1
2. Design
20
Γ𝑖𝑛 > 1 Γ𝑖𝑛 < 1
Γ𝑖𝑛 > 1Γ𝑖𝑛 < 1
Unconditional Stability Unconditional Unstability
Stability
• Border which delimits between stable and unstable regions:
 Γ𝑖𝑛 = 𝑆11 +
𝑆12 𝑆21Γ 𝐿
1−𝑆22Γ 𝐿
= 1 Γ𝑜𝑢𝑡 = 𝑆22 +
𝑆12 𝑆21Γ 𝑆
1−𝑆11Γ 𝑆
= 1
2. Design
21
Γ𝑖𝑛 > 1
Γ𝑖𝑛 < 1
Γ𝑖𝑛 < 1
Γ𝑖𝑛 > 1
Stability
2. Design
22
• Stability circles @ 𝑓0 → Potentially unstable
• Dashed lines → Unstable region
Stability Factor: K-Δ Test
• It is convenient to have a design with 𝐾 𝑓 > 1 in a
reasonable BW
𝑲 =
𝟏 − 𝑺 𝟏𝟏
𝟐 − 𝑺 𝟐𝟐
𝟐 + ∆ 𝟐
𝟐 𝑺 𝟏𝟐 𝑺 𝟐𝟏
> 𝟏
∆ = 𝑺 𝟏𝟏 𝑺 𝟐𝟐 − 𝑺 𝟏𝟐 𝑺 𝟐𝟏 < 𝟏
2. Design
23
Stabilization methods
2. Design
24
50 2050 4050 6050 8050 10000
Frequency (MHz)
Initial K Factor
0
2
4
6
8
2450 MHz
4.424
2450 MHz
0.5643
K (no resistor)
K (gate resistor)
Unilateral Approximation
2. Design
25
𝑈 =
𝑆11 𝑆12 𝑆21 𝑆22
1 − 𝑆11
2 1 − 𝑆22
2
−20 log 1 + 𝑈 < 𝐺 𝑇 − 𝐺 𝑇𝑈 𝑑𝐵 < −20 log 1 − 𝑈
Maximum gain design.
Bilateral case:
• Γ𝐼𝑁 = 𝑆11 +
𝑆12 𝑆21 𝚪𝑳
1−𝑆22 𝚪𝑳
= Γ𝑆
∗
• Γ𝑂𝑈𝑇 = 𝑆22 +
𝑆12 𝑆21 𝚪𝑺
1−𝑆11 𝚪𝑺
= Γ𝐿
∗
Maximum gain design.
Unilateral case:
• Γ𝐼𝑁 = 𝑆11 = Γ𝑆
∗
• Γ𝑂𝑈𝑇 = 𝑆22 = Γ𝐿
∗
2-Port Device11S 22S
21S
?012 S
−3.7225 𝑑𝐵 < 𝐺 𝑇 − 𝐺 𝑇𝑈 𝑑𝐵 < 4.5775 𝑑𝐵
Load-Pull
2. Design
26
Process whereby a set of points of the Smith Chart are evaluated in
terms of good performance as potential candidates to be the final
reflection coefficient for the Output Matching Network.
Load-Pull
2. Design
27
DCVS
ID=VDS
V=28 VDCVS
ID=VGS
V=-2.2 V
V_METER
ID=Vd
V_METER
ID=Vg
I_METER
ID=Ig
I_METER
ID=Id
Xo Xn. . .
SWPVAR
ID=Bias
VarName="iBias"
Values=stepped(3,4,0.5)
UnitType=None
Xo Xn. . .
SWPVAR
ID=GammaL3
VarName="iGammaL3"
Values=stepped(-180,180,60)
UnitType=None
Xo Xn. . .
SWPVAR
ID=GammaL2
VarName="iGammaL2"
Values=stepped(0,360,90)
UnitType=None
TrVi Ii
S
1 2
3
4 5 6
CGH40010F_R6_VA
ID=Q1
Tbase=25
Rth=8
3:Bias
12
LTUNER2
ID=SourceTuner1
Mag=0.5
Ang=0 Deg
Zo=50 Ohm
3:Bias
1 2
LTUNER2
ID=LoadTuner1
Mag=0.5
Ang=0 Deg
Zo=50 Ohm
PORT
P=2
Z=50 Ohm
PORT_PS1
P=1
Z=50 Ohm
PStart=0.600000000000001 dBm
PStop=30.6 dBm
PStep=1 dB
7
⦁ Attach gate / base current & voltage meters to desired device pin
⦁ Attach drain / collector current & voltage meters to desired device pins
⦁ Note that current should always defined into the desired pin
4
⦁ Set the Source Tuner to
the desired impedance.
⦁ For 50 Ohms, set:
Mag1 = 0
Ang1 = 0
2
⦁ Set power sweep
⦁ Disable power sweep by
replacing with PORT1
1
⦁ Enable / Disable SWPVAR blocks based on your needs
⦁ Set enabled SWPVAR sweep values
⦁ Do not change any swept variable names.
⦁ Contact technical support to sweep additional
variables
6
⦁ Replace with your DUT
iBias=3
iGammaL3=0iGammaL2=0
5
⦁ Replace DCVS with
DCCS as needed
⦁ Do not delete any of the tuners or voltage and current meters; they are all needed for load pull simulation due to the switch to A/B wave file formats
⦁ It is okay to rename this schematic
3
⦁ Set schematic frequencies
under schematic options
• AWR has its own script that automates the process
• Source-Pull is still in beta phase → Γ𝑆 = Γ𝑖𝑛
∗
Load-Pull
2. Design
28
Once the Load-Pull has been performed, the points that agree with the design
specifications are chosen.
LTUNER
ID=TU1
Mag=0.44152
Ang=149.3904Deg
Zo=50 Ohm
TLIN
ID=50
Z0=50 Ohm
EL=47Deg
F0=2450MHz
CAP
ID=C1
C=50pF
TLIN
ID=TL1
Z0=50 Ohm
EL=45Deg
F0=2450MHz
OPEN
ID=J1
PORT
P=1
Z=50Ohm
PORT
P=2
Z=50Ohm
PORT
P=3
Z=50Ohm
PORT
P=4
Z=50Ohm
Γ𝑜𝑢𝑡 = 0.44152∠149.3904°
LTUNER
ID=TU1
Mag=0.44152
Ang=149.3904Deg
Zo=50 Ohm
TLIN
ID=50
Z0=50 Ohm
EL=47Deg
F0=2450MHz
CAP
ID=C1
C=50pF
TLIN
ID=TL1
Z0=50 Ohm
EL=45Deg
F0=2450MHz
OPEN
ID=J1
PORT
P=1
Z=50Ohm
PORT
P=2
Z=50Ohm
PORT
P=3
Z=50Ohm
PORT
P=4
Z=50Ohm
Load-Pull
2. Design
29
𝑍𝑖𝑛 = 𝑍0
𝑍 𝐿 + 𝑗𝑍0tan(𝛽𝑙)
𝑍0 + 𝑗𝑍 𝐿tan(𝛽𝑙)
0
1.0-1.01.0
10.0
-10.0
10.0
5.0
-5.0
5.0
2.0
-2.02.0
3.0
-3.0
3.0
4.0
-4.0
4.0
0.2
-0.2
0.2
0.4
-0.4
0.4
0.6
-0.60.6
0.8
-0.80.8
0
1.01.0-1.0
10.0
10.0
-10.0
5.0
5.0
-5.0
2.0
2.0-2.0
3.0
3.0
-3.0
4.0
4.0
-4.0
0.2
0.2
-0.2
0.4
0.4
-0.4
0.6
0.6-0.6
0.8
0.8-0.8
OMN
Swp Max
2450MHz
Swp Min
2450MHz
Series TXLine
Open STUB
Γ𝑜𝑢𝑡𝚪𝒐𝒖𝒕 Γ1
𝚪𝟏
Input Matching Network
2. Design
30
• Conjugate Matching
Γ𝑆 = Γ𝑖𝑛
∗
TLIN
ID=TL2
Z0=17.93 Ohm
EL=24.3 Deg
F0=2450 MHz
OPEN
ID=J1
TLIN
ID=TL1
Z0=48.27 Ohm
EL=65.7 Deg
F0=2450 MHz
PORT
P=1
Z=50 Ohm
PORT
P=2
Z=50 Ohm
Bias Network
2. Design
31
• Critical design part in order to avoid RF leakage through the
bias network.
• Many possible configurations:
a. Low BW
b. Acceptable BW
c. Good BW and reduced size
Bias Network
2. Design
32
TrVi Ii
S
1 2
3
4 5 6
CGH40010F_R6_VA
ID=Q1
Tbase=25
Rth=8 V_METER
ID=Vd1
I_METER
ID=Ig1
CAP
ID=C2
C=20pF
I_METER
ID=I_in1
MLIN
ID=TL6
W=2.1394617455677mm
L=9.00788441856134mm
MSUB=RO_RO4350B1
MLIN
ID=TL7
W=1.13179mm
L=18.2827939523261mm
MSUB=RO_RO4350B1
MLIN
ID=TL14
W=1.13179mm
L=8.42648946346399mm
MSUB=RO_RO4350B1
MLIN
ID=TL20
W=1.13179mm
L=3.44366958458732mm
MSUB=RO_RO4350B1
MLIN
ID=TL27
W=1.13179mm
L=6.2mm
MSUB=RO_RO4350B1
MLIN
ID=TL28
W=1.13179mm
L=3.9182030314894mm
MSUB=RO_RO4350B1
MOPEN$
ID=TL12
MSUB=RO_RO4350B1
1 2
3
MTEE$
ID=TL15
MSUB=RO_RO4350B1
RES
ID=R1
R=6.81Ohm
1 2
1 2
GPROBE2
ID=GP1
V_METER
ID=Vd2
I_METER
ID=Id2
V_ME
ID=VM
12
3
MTEE$
ID=TL13
MSUB=RO_RO4350B1
CAP
ID=C5
C=47000pF
DCVS
ID=Vgs1
V=-2.2V
MLIN
ID=TL4
W=W_TLStubmm
L=L_TL2Stubmm
MSUB=RO_RO4350B1
MLIN
ID=TL22
W=1.09377006058279mm
L=1.0929717637931mm
MSUB=RO_RO4350B1
MLIN
ID=TL23
W=5mm
L=5mm
MSUB=RO_RO4350B1
MLIN
ID=TL26
W=1.11213944458008mm
L=2.49627311533999mm
MSUB=RO_RO4350B1
MSRSTUB2
ID=ST1
Ro=Ro_stubmm
Wg=Wg_stubmm
W=W_TLStubmm
Theta=Theta_stubDeg
MSUB=RO_RO4350B1
1
2
3
MTEE$
ID=TL9
MSUB=RO_RO4350B1
MVIA1P
ID=V4
D=1mm
H=0.52578mm
T=0.017mm
W=5mm
RHO=0.7
MSUB=RO_RO4350B1
RES
ID=R2
R=37.4Ohm
MLIN
ID=TL8
W=W_TLStubmm
L=L_TL1Stubmm
MSUB=RO_RO4350B1
PORT_PS1
P=1
Z=50Ohm
PStart=0dBm
PStop=40dBm
PStep=1dB
PORT1
P=1
Z=50Ohm
Pwr=10dBm
Conn_ViConn_Ii
Low Freq. Stabilization
Resistor
Bypass Capacitor
Final design
2. Design
33
TrVi Ii
S
1 2
3
4 5 6
CGH40010F_R6_VA
ID=Q1
Tbase=25
Rth=8
I_METER
ID=Ig1
CAP
ID=C2
C=20 pF
I_METER
ID=I_in1
MLIN
ID=TL6
W=2.1394617455677 mm
L=9.00788441856134 mm
MSUB=RO_RO4350B1
MLIN
ID=TL7
W=1.13179 mm
L=18.2827939523261 mm
MSUB=RO_RO4350B1
MLIN
ID=TL14
W=1.13179 mm
L=8.42648946346399 mm
MSUB=RO_RO4350B1
MLIN
ID=TL20
W=1.13179 mm
L=3.44366958458732 mm
MSUB=RO_RO4350B1
MLIN
ID=TL27
W=1.13179 mm
L=6.2 mm
MSUB=RO_RO4350B1
MLIN
ID=TL28
W=1.13179 mm
L=3.9182030314894 mm
MSUB=RO_RO4350B1
MOPEN$
ID=TL12
MSUB=RO_RO4350B1
1 2
3
MTEE$
ID=TL15
MSUB=RO_RO4350B1
RES
ID=R1
R=6.81 Ohm
1 2
1 2
GPROBE2
ID=GP1
V_METER
ID=Vd2
I_METER
ID=Id2
12
3
MTEE$
ID=TL13
MSUB=RO_RO4350B1
MLIN
ID=TL4
W=W_TLStub mm
L=L_TL2Stub mm
MSUB=RO_RO4350B1
MLIN
ID=TL22
W=1.09377006058279 mm
L=1.0929717637931 mm
MSUB=RO_RO4350B1
MLIN
ID=TL26
W=1.11213944458008 mm
L=2.49627311533999 mm
MSUB=RO_RO4350B1
MSRSTUB2
ID=ST1
Ro=Ro_stub mm
Wg=Wg_stub mm
W=W_TLStub mm
Theta=Theta_stub Deg
MSUB=RO_RO4350B1
1
2
3
MTEE$
ID=TL9
MSUB=RO_RO4350B1
RES
ID=R2
R=37.4 Ohm
MLIN
ID=TL8
W=W_TLStub mm
L=L_TL1Stub mm
MSUB=RO_RO4350B1
PORT_PS1
P=1
Z=50 Ohm
PStart=0 dBm
PStop=40 dBm
PStep=1 dB
PORT1
P=1
Z=50 Ohm
Pwr=10 dBm
Conn_ViConn_Ii
CAP
ID=C1
C=47 pF
MLIN
ID=TL1
W=1.13179 mm
L=9.1 mm
MSUB=RO_RO4350B1
MLIN
ID=TL2
W=1.15424925832038 mm
L=8.8091341147881 mm
MSUB=RO_RO4350B1
MLIN
ID=TL3
W=1.13179 mm
L=2.83546915660083 mm
MSUB=RO_RO4350B1
MLIN
ID=TL5
W=W_DoubleStub mm
L=L_DoubleStub mm
MSUB=RO_RO4350B1
MLIN
ID=TL11
W=W_DoubleStub mm
L=L_DoubleStub mm
MSUB=RO_RO4350B1
MLIN
ID=TL17
W=1.13179 mm
L=1.83798534101102 mm
MSUB=RO_RO4350B1
MLIN
ID=TL19
W=1.13179 mm
L=3.27959942836177 mm
MSUB=RO_RO4350B1
MLIN
ID=TL25
W=1.13179 mm
L=2.36734037034666 mm
MSUB=RO_RO4350B1
MLIN
ID=TL34
W=W_TLStub mm
L=L_TL1Stub mm
MSUB=RO_RO4350B1
MOPEN$
ID=TL10
MSUB=RO_RO4350B1
MOPEN$
ID=TL18
MSUB=RO_RO4350B1
MOPEN$
ID=TL33
MSUB=RO_RO4350B1
MSRSTUB2
ID=ST3
Ro=Ro_stub mm
Wg=Wg_stub mm
W=W_TLStub mm
Theta=Theta_stub Deg
MSUB=RO_RO4350B1
12
3
MTEE$
ID=TL16
MSUB=RO_RO4350B1
1 2
3
MTEE$
ID=TL24
MSUB=RO_RO4350B1
1 2
1 2
GPROBE2
ID=GP2
1
2
3
4
MCROSSX$
ID=MX1
MSUB=RO_RO4350B1
PORT
P=2
Z=50 Ohm
Input Matching
Network
Output Matching
Network
• Some changes were made after using real transmission lines
Final design
2. Design
34
• RO4350B substrate with low thickness to take care about termal conductivity
50 2050 4050 6050 8050 10000
Frequency (MHz)
Rollet's Condition in Final Design
0
5
10
15
20
0
0.5
1
1.5
2
K (L)
B1 (R)
2000 2200 2400 2600 2800 3000
Frequency (MHz)
S-Parameters of the PA
-35
-30
-25
-20
-15
-10
-5
0
-5
-1.429
2.143
5.714
9.286
12.86
16.43
20
2450MHz
2506 MHz
-10 dB
2392 MHz
-10 dB
2450 MHz
-27.67 dB
2450 MHz
15 dB
S11(dB) (L)
S21(dB) (R)
S12(dB) (L)
S22(dB) (L)
0 10 20 30 40
Power (dBm)
Comparison
0
5
10
15
20
Gain(dB)
10
20
30
40
50
Pout(dBm)
0
20
40
60
80PAE(%)
26.16dBm
26.16 dBm
40.16 dBm
26.16 dBm
53.3
26.16 dBm
14 dB
PAE After
PAE Before
Pout After (dBm)
Pout Before (dBm)
Gain(dB) After
Gain(dB) Before
2. Design
35
• RO4350B substrate with low thickness to take care about termal conductivity
Final design
RF OUTRF IN
Outline
1. Introduction
2. Design
3. Manufacturing
4. Results
5. Conclusions and Future work
Heat Sink Selection
3. Manufacturing
37
𝜃𝑗𝑎 = 𝜃𝑗𝑐 + 𝜃𝑐𝑠 + 𝜃𝑠𝑎 =
𝑇𝑗 − 𝑇𝑎
𝑄
= 14.8192 º𝐶/𝑊
𝜃𝑐𝑠 =
𝜌 · 𝑡
𝐴
= 0.5 º𝐶/𝑊 (𝑇𝑦𝑝. 𝑖𝑛 𝑡ℎ𝑒𝑟𝑚𝑎𝑙 𝑐𝑜𝑚𝑝𝑜𝑢𝑛𝑑)
𝜃𝑠𝑎 =
𝑇𝑗 − 𝑇𝑎
𝑄
− (𝜃jc + 𝜃𝑐𝑠)
𝜃𝑗𝑐 = 8.0 º𝐶/𝑊 (𝑇𝑟𝑎𝑛𝑠𝑖𝑠𝑡𝑜𝑟 𝐷𝑎𝑡𝑎𝑠ℎ𝑒𝑒𝑡)
𝜃𝑠𝑎𝑀𝑎𝑥 = 6.31921 º 𝐶 𝑊
Heat Sink Selection
3. Manufacturing
38
𝜃 )𝑠𝑎 (641𝑘 ≃ 2.43 º 𝐶 𝑊
Assembly
3. Manufacturing
39
Assembly
3. Manufacturing
40
Outline
1. Introduction
2. Design
3. Manufacturing
4. Results
5. Conclusions and Future work
4. Results
42
4. Results
43
• To correct the frequency shift:
𝑅𝑒𝑠𝑖𝑧𝑒 𝑓𝑎𝑐𝑡𝑜𝑟 =
𝑓𝑠ℎ𝑖𝑓𝑡𝑒𝑑
𝑓0
=
2200
2450
=
44
49
≃ 0.898
4. Results
Inconvenients and unexpected stuff
After 4 minutes working, the transistor was BURNT!
Potential causes:
a. Thermal compound
b. Q-Point too close to the maximum dissipation curve
c. Testing with LOW Input Power. LOW PAE. HIGH dissipation
d. When frequency shift occurs, at 2.45GHz we have a totally different behaviour
• IT HAS NOT BEEN POSSIBLE TO MEASURE ANYMORE
44
Outline
1. Introduction
2. Design
3. Manufacturing
4. Results
5. Conclusions and Future work
Conclusions
• Initial thermal analysis is critical
• Project with high didactic potential
Future Work
• Fix the overheating issue
• Design other amplifier classes such as AB and B to be
able to compare its performance, efficiency and so
forth
5. Conclusions and Future Work
46
Any Question?

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Design Basics on Power Amplifiers

  • 1. Design Basics on Power Amplifiers Wednesday, 16th December 2015
  • 2. Outline 1. Introduction 2. Design 3. Manufacturing 4. Results 5. Conclusions and Future work
  • 3. What is amplification? 1. Introduction 3 The operation of an electronic device increasing the power of a signal.
  • 4. Amplifiers depending on operating frequency 1. Introduction 4 Low frequency High frequency or RF
  • 5. Transistor Input Matching Network Output Matching Network Bias Network (Gate) Bias Network (Drain) RF in RF out Vgs Vds 1. Introduction 5 Basic Microwave Amplifier scheme
  • 6. 1. Introduction 6 Main concepts to work with: • Linearity: capability of an amplifier to reproduce increased exact copies of the input signal. • Efficiency: how much of the DC power supplied to the amplifier is transformed into amplification. They are in inverse proportion. These characteristics determine the class of the amplifier!
  • 7. Transistor Characteristic IV Curves 1. Introduction 7 𝑉𝐶𝐸 𝐼 𝐶 𝐼 𝐵 = 100 𝜇𝐴 10 𝑚𝐴 C (Collector) or D (Drain) E (Emitter) or S (Source) B (Base) or G (Gate) 20 V + _ 𝑉𝐶𝐸 𝐼 𝐶 𝑰 𝑩
  • 8. Load-line 1. Introduction 8 DC equivalent AC equivalent 𝑉𝐶𝐸 𝐼 𝐶 𝑉𝐶𝐶 − 𝑉𝑅 𝐶 − 𝑉𝐶𝐸 − 𝑉𝑅 𝐸 = 0 𝑉𝐶𝐶 − 𝐼 𝐶 𝑅 𝐶 − 𝑉𝐶𝐸 − 𝐼 𝐸 𝑅 𝐸 = 0 𝑉𝐶𝐶 − 𝐼 𝐶(𝑅 𝐶+𝑅 𝐸) − 𝑉𝐶𝐸 = 0 Load-line equation (y = mx+n): 𝐼 𝐶 = − 1 𝑅 𝐶 + 𝑅 𝐸 𝑉𝐶𝐸 + 𝑉𝐶𝐶 𝑅 𝐶 + 𝑅 𝐸 In saturation… 𝑉𝐶𝐸 ≈ 0Cut-off… 𝐼 𝐶 ≈ 0 𝑉𝐶𝐶 𝑅 𝐶 + 𝑅 𝐸 𝑉𝐶𝐶 Q-Point
  • 9. Load-line 1. Introduction 9 DC equivalent AC equivalent 𝑣 𝐶𝐸 = −𝑖 𝐶 𝑟𝐶 𝑉𝐶𝐸 − 𝑉𝐶𝐸𝑄 = − 𝐼 𝐶 − 𝐼 𝐶𝑄 𝑟𝐶 Load-line equation (y = mx+n): 𝐼 𝐶 = − 1 𝑟𝐶 𝑉𝐶𝐸 + 𝑉𝐶𝐸𝑄 𝑟𝐶 + 𝐼 𝐶𝑄 𝑖 𝐶 𝑉𝐶𝐸 In saturation… 𝑉𝐶𝐸 ≈ 0In Cut-off… 𝐼 𝐶 ≈ 0 Q-Point 𝑰 𝑪𝑸 + 𝑽 𝑪𝑬𝑸 𝒓 𝑪 𝑽 𝑪𝑬𝑸 + 𝑰 𝑪𝑸 𝒓 𝑪 𝐼 𝐶
  • 10. Load-line 1. Introduction 10 Q-Point 𝑰 𝑪𝑸 + 𝑽 𝑪𝑬𝑸 𝒓 𝑪 𝑽 𝑪𝑬𝑸 + 𝑰 𝑪𝑸 𝒓 𝑪 𝑉𝐶𝐸 𝐼 𝐶 𝑣𝐶𝐸/𝐷𝑆≡𝑣𝑅𝐹𝑜𝑢𝑡 𝑖 𝐶𝐸/𝐷𝑆 ≡ 𝑖 𝑅𝐹𝑜𝑢𝑡
  • 11. Power Amplifier Classes 1. Introduction 11 Class Conduction Angle A θ = 2π AB π < θ < 2π B θ = π C θ < π D – T θ ≈ 0
  • 12. Power Amplifier Classes 1. Introduction 12 Clase A Clase B Clase AB Clase C
  • 13. Power Amplifier Classes 1. Introduction 13
  • 14. Outline 1. Introduction 2. Design 3. Manufacturing 4. Results 5. Conclusions and Future work
  • 15. Transistor Tecnology Selection • GaN HEMT:  High Efficiency  High Gain  Great Bandwidth  Low Power Consumption  Selección del Transistor • CGH40010F (Cree Inc.) 2. Design 15
  • 16. IV Characteristics and Q-Point 2. Design 16 0 30 60 84 Vds (V) IV Curves 0 500 1000 1500 2000 2400 Ids(mA) IV Curves (mA) Q-Point (28V, 482mA) 𝑽 𝑮𝑺 = −𝟐. 𝟐𝑽 TrVi Ii S 1 2 3 4 5 6 CGH40010F_R6_VA ID=Q1 Tbase=25 Rth=8 Swp Step IVCURVE ID=IV1 VSWEEP_start=0 V VSWEEP_stop=84 V VSWEEP_step=1 V VSTEP_start=-10 V VSTEP_stop=2 V VSTEP_step=0.2 V • Maximum drain voltage (84 V) • Maximum drain current (1500 mA) • Cut-off threshold (67 mA) • Saturation threshold • Maximum dissipated power (14 W)
  • 17. Dynamic/AC Load-line 2. Design 17 TrVi Ii S 1 2 3 4 5 6 CGH40010F_R6_VA ID=Q1 Tbase=25 Rth=8 0.000399mA -2.2V 482mA 28V 482mA 0V 0mA 27.7V 482mA 0V 0mA 107V I_METER ID=Id_intr 482mA V_METER ID=Vd_intr DCVS ID=Vgs V=-2.2 V 0.000398mA -2.2V I_METER ID=I_in 0mA 0V 0V I_METER ID=Ig 0.000399mA -2.2V DCVS ID=Vdc V=28 V 482mA 28V V_METER ID=Vd I_METER ID=Id 482mA 28V 3:Bias 12 LTUNER2 ID=TU3 Mag=0 Ang=0 Deg Zo=50 Ohm 0.000399mA0mA 0.000398mA 3:Bias 1 2 LTUNER2 ID=TU1 Mag=0 Ang=0 Deg Zo=50 Ohm 482mA 0mA 0V 482mA V_METER ID=VM_trise PORT P=2 Z=50 Ohm 0mA PORT_PS1 P=1 Z=50 Ohm PStart=0.6 dBm PStop=40.6 dBm PStep=1 dB 0mA PORT1 P=1 Z=50 Ohm Pwr=27.6 dBm Conn_Vi 27.7V Conn_Vi 27.7V Conn_Ii 0V Conn_Ii 0V 0 30 60 84 Vds (V) IV Curves 0 500 1000 1500 2000 2400 Ids(mA) 28 V 482.3 mA Vstep = -2.2 V IV Curves (mA) DLL @ 7.6dBm (mA) DLL @ 17.6dBm (mA) DLL @ P1dB (mA) 0 0.3 0.6 0.816 Time (ns) RF in VS. RF out -600 -400 -200 0 200 400 600 P1dBInputPower -300 -200 -100 0 100 200 300 20dBmInputPower RF IN @ 20dBm (mA) RF OUT @ 20dBm (mA) RF IN @ P1dB (mA) RF OUT @ P1dB (mA) 0 V I_METER ID=Ig 0.000399 mA -2.2 V 3:Bias 12 LTUNER2 ID=TU3 Mag=0 Ang=0 Deg Zo=50 Ohm 0.000399 mA0 mA
  • 18. Gain, Output Power and PAE 2. Design 18 0.6 10.6 20.6 30.6 40.6 Power (dBm) Pin VS Pout and Gain 0 10 20 30 40 50 27.6 dBm 10.9 dB 18.52 dBm 11.89 dB Pout (dBm) PGain (dB) PAE (%)
  • 19. Stability • Critical factor in order to avoid oscillations (Γ > 1) • This is due to the negative either input or output resistance 2. Design 19 𝑅𝑒 𝑍 𝑆 + 𝑍𝑖𝑛 < 0 𝑅𝑒 𝑍 𝑜𝑢𝑡 + 𝑍 𝐿 < 0 Transistor Input Matching Network Output Matching Network S in out L 0Z 0Z 𝑍 = 𝑍0 1 + Γ 1 − Γ
  • 20. Conditional Stability Stability • Border which delimits between stable and unstable regions:  Γ𝑖𝑛 = 𝑆11 + 𝑆12 𝑆21Γ 𝐿 1−𝑆22Γ 𝐿 = 1 Γ𝑜𝑢𝑡 = 𝑆22 + 𝑆12 𝑆21Γ 𝑆 1−𝑆11Γ 𝑆 = 1 2. Design 20 Γ𝑖𝑛 > 1 Γ𝑖𝑛 < 1 Γ𝑖𝑛 > 1Γ𝑖𝑛 < 1
  • 21. Unconditional Stability Unconditional Unstability Stability • Border which delimits between stable and unstable regions:  Γ𝑖𝑛 = 𝑆11 + 𝑆12 𝑆21Γ 𝐿 1−𝑆22Γ 𝐿 = 1 Γ𝑜𝑢𝑡 = 𝑆22 + 𝑆12 𝑆21Γ 𝑆 1−𝑆11Γ 𝑆 = 1 2. Design 21 Γ𝑖𝑛 > 1 Γ𝑖𝑛 < 1 Γ𝑖𝑛 < 1 Γ𝑖𝑛 > 1
  • 22. Stability 2. Design 22 • Stability circles @ 𝑓0 → Potentially unstable • Dashed lines → Unstable region
  • 23. Stability Factor: K-Δ Test • It is convenient to have a design with 𝐾 𝑓 > 1 in a reasonable BW 𝑲 = 𝟏 − 𝑺 𝟏𝟏 𝟐 − 𝑺 𝟐𝟐 𝟐 + ∆ 𝟐 𝟐 𝑺 𝟏𝟐 𝑺 𝟐𝟏 > 𝟏 ∆ = 𝑺 𝟏𝟏 𝑺 𝟐𝟐 − 𝑺 𝟏𝟐 𝑺 𝟐𝟏 < 𝟏 2. Design 23
  • 24. Stabilization methods 2. Design 24 50 2050 4050 6050 8050 10000 Frequency (MHz) Initial K Factor 0 2 4 6 8 2450 MHz 4.424 2450 MHz 0.5643 K (no resistor) K (gate resistor)
  • 25. Unilateral Approximation 2. Design 25 𝑈 = 𝑆11 𝑆12 𝑆21 𝑆22 1 − 𝑆11 2 1 − 𝑆22 2 −20 log 1 + 𝑈 < 𝐺 𝑇 − 𝐺 𝑇𝑈 𝑑𝐵 < −20 log 1 − 𝑈 Maximum gain design. Bilateral case: • Γ𝐼𝑁 = 𝑆11 + 𝑆12 𝑆21 𝚪𝑳 1−𝑆22 𝚪𝑳 = Γ𝑆 ∗ • Γ𝑂𝑈𝑇 = 𝑆22 + 𝑆12 𝑆21 𝚪𝑺 1−𝑆11 𝚪𝑺 = Γ𝐿 ∗ Maximum gain design. Unilateral case: • Γ𝐼𝑁 = 𝑆11 = Γ𝑆 ∗ • Γ𝑂𝑈𝑇 = 𝑆22 = Γ𝐿 ∗ 2-Port Device11S 22S 21S ?012 S −3.7225 𝑑𝐵 < 𝐺 𝑇 − 𝐺 𝑇𝑈 𝑑𝐵 < 4.5775 𝑑𝐵
  • 26. Load-Pull 2. Design 26 Process whereby a set of points of the Smith Chart are evaluated in terms of good performance as potential candidates to be the final reflection coefficient for the Output Matching Network.
  • 27. Load-Pull 2. Design 27 DCVS ID=VDS V=28 VDCVS ID=VGS V=-2.2 V V_METER ID=Vd V_METER ID=Vg I_METER ID=Ig I_METER ID=Id Xo Xn. . . SWPVAR ID=Bias VarName="iBias" Values=stepped(3,4,0.5) UnitType=None Xo Xn. . . SWPVAR ID=GammaL3 VarName="iGammaL3" Values=stepped(-180,180,60) UnitType=None Xo Xn. . . SWPVAR ID=GammaL2 VarName="iGammaL2" Values=stepped(0,360,90) UnitType=None TrVi Ii S 1 2 3 4 5 6 CGH40010F_R6_VA ID=Q1 Tbase=25 Rth=8 3:Bias 12 LTUNER2 ID=SourceTuner1 Mag=0.5 Ang=0 Deg Zo=50 Ohm 3:Bias 1 2 LTUNER2 ID=LoadTuner1 Mag=0.5 Ang=0 Deg Zo=50 Ohm PORT P=2 Z=50 Ohm PORT_PS1 P=1 Z=50 Ohm PStart=0.600000000000001 dBm PStop=30.6 dBm PStep=1 dB 7 ⦁ Attach gate / base current & voltage meters to desired device pin ⦁ Attach drain / collector current & voltage meters to desired device pins ⦁ Note that current should always defined into the desired pin 4 ⦁ Set the Source Tuner to the desired impedance. ⦁ For 50 Ohms, set: Mag1 = 0 Ang1 = 0 2 ⦁ Set power sweep ⦁ Disable power sweep by replacing with PORT1 1 ⦁ Enable / Disable SWPVAR blocks based on your needs ⦁ Set enabled SWPVAR sweep values ⦁ Do not change any swept variable names. ⦁ Contact technical support to sweep additional variables 6 ⦁ Replace with your DUT iBias=3 iGammaL3=0iGammaL2=0 5 ⦁ Replace DCVS with DCCS as needed ⦁ Do not delete any of the tuners or voltage and current meters; they are all needed for load pull simulation due to the switch to A/B wave file formats ⦁ It is okay to rename this schematic 3 ⦁ Set schematic frequencies under schematic options • AWR has its own script that automates the process • Source-Pull is still in beta phase → Γ𝑆 = Γ𝑖𝑛 ∗
  • 28. Load-Pull 2. Design 28 Once the Load-Pull has been performed, the points that agree with the design specifications are chosen. LTUNER ID=TU1 Mag=0.44152 Ang=149.3904Deg Zo=50 Ohm TLIN ID=50 Z0=50 Ohm EL=47Deg F0=2450MHz CAP ID=C1 C=50pF TLIN ID=TL1 Z0=50 Ohm EL=45Deg F0=2450MHz OPEN ID=J1 PORT P=1 Z=50Ohm PORT P=2 Z=50Ohm PORT P=3 Z=50Ohm PORT P=4 Z=50Ohm Γ𝑜𝑢𝑡 = 0.44152∠149.3904°
  • 29. LTUNER ID=TU1 Mag=0.44152 Ang=149.3904Deg Zo=50 Ohm TLIN ID=50 Z0=50 Ohm EL=47Deg F0=2450MHz CAP ID=C1 C=50pF TLIN ID=TL1 Z0=50 Ohm EL=45Deg F0=2450MHz OPEN ID=J1 PORT P=1 Z=50Ohm PORT P=2 Z=50Ohm PORT P=3 Z=50Ohm PORT P=4 Z=50Ohm Load-Pull 2. Design 29 𝑍𝑖𝑛 = 𝑍0 𝑍 𝐿 + 𝑗𝑍0tan(𝛽𝑙) 𝑍0 + 𝑗𝑍 𝐿tan(𝛽𝑙) 0 1.0-1.01.0 10.0 -10.0 10.0 5.0 -5.0 5.0 2.0 -2.02.0 3.0 -3.0 3.0 4.0 -4.0 4.0 0.2 -0.2 0.2 0.4 -0.4 0.4 0.6 -0.60.6 0.8 -0.80.8 0 1.01.0-1.0 10.0 10.0 -10.0 5.0 5.0 -5.0 2.0 2.0-2.0 3.0 3.0 -3.0 4.0 4.0 -4.0 0.2 0.2 -0.2 0.4 0.4 -0.4 0.6 0.6-0.6 0.8 0.8-0.8 OMN Swp Max 2450MHz Swp Min 2450MHz Series TXLine Open STUB Γ𝑜𝑢𝑡𝚪𝒐𝒖𝒕 Γ1 𝚪𝟏
  • 30. Input Matching Network 2. Design 30 • Conjugate Matching Γ𝑆 = Γ𝑖𝑛 ∗ TLIN ID=TL2 Z0=17.93 Ohm EL=24.3 Deg F0=2450 MHz OPEN ID=J1 TLIN ID=TL1 Z0=48.27 Ohm EL=65.7 Deg F0=2450 MHz PORT P=1 Z=50 Ohm PORT P=2 Z=50 Ohm
  • 31. Bias Network 2. Design 31 • Critical design part in order to avoid RF leakage through the bias network. • Many possible configurations: a. Low BW b. Acceptable BW c. Good BW and reduced size
  • 32. Bias Network 2. Design 32 TrVi Ii S 1 2 3 4 5 6 CGH40010F_R6_VA ID=Q1 Tbase=25 Rth=8 V_METER ID=Vd1 I_METER ID=Ig1 CAP ID=C2 C=20pF I_METER ID=I_in1 MLIN ID=TL6 W=2.1394617455677mm L=9.00788441856134mm MSUB=RO_RO4350B1 MLIN ID=TL7 W=1.13179mm L=18.2827939523261mm MSUB=RO_RO4350B1 MLIN ID=TL14 W=1.13179mm L=8.42648946346399mm MSUB=RO_RO4350B1 MLIN ID=TL20 W=1.13179mm L=3.44366958458732mm MSUB=RO_RO4350B1 MLIN ID=TL27 W=1.13179mm L=6.2mm MSUB=RO_RO4350B1 MLIN ID=TL28 W=1.13179mm L=3.9182030314894mm MSUB=RO_RO4350B1 MOPEN$ ID=TL12 MSUB=RO_RO4350B1 1 2 3 MTEE$ ID=TL15 MSUB=RO_RO4350B1 RES ID=R1 R=6.81Ohm 1 2 1 2 GPROBE2 ID=GP1 V_METER ID=Vd2 I_METER ID=Id2 V_ME ID=VM 12 3 MTEE$ ID=TL13 MSUB=RO_RO4350B1 CAP ID=C5 C=47000pF DCVS ID=Vgs1 V=-2.2V MLIN ID=TL4 W=W_TLStubmm L=L_TL2Stubmm MSUB=RO_RO4350B1 MLIN ID=TL22 W=1.09377006058279mm L=1.0929717637931mm MSUB=RO_RO4350B1 MLIN ID=TL23 W=5mm L=5mm MSUB=RO_RO4350B1 MLIN ID=TL26 W=1.11213944458008mm L=2.49627311533999mm MSUB=RO_RO4350B1 MSRSTUB2 ID=ST1 Ro=Ro_stubmm Wg=Wg_stubmm W=W_TLStubmm Theta=Theta_stubDeg MSUB=RO_RO4350B1 1 2 3 MTEE$ ID=TL9 MSUB=RO_RO4350B1 MVIA1P ID=V4 D=1mm H=0.52578mm T=0.017mm W=5mm RHO=0.7 MSUB=RO_RO4350B1 RES ID=R2 R=37.4Ohm MLIN ID=TL8 W=W_TLStubmm L=L_TL1Stubmm MSUB=RO_RO4350B1 PORT_PS1 P=1 Z=50Ohm PStart=0dBm PStop=40dBm PStep=1dB PORT1 P=1 Z=50Ohm Pwr=10dBm Conn_ViConn_Ii Low Freq. Stabilization Resistor Bypass Capacitor
  • 33. Final design 2. Design 33 TrVi Ii S 1 2 3 4 5 6 CGH40010F_R6_VA ID=Q1 Tbase=25 Rth=8 I_METER ID=Ig1 CAP ID=C2 C=20 pF I_METER ID=I_in1 MLIN ID=TL6 W=2.1394617455677 mm L=9.00788441856134 mm MSUB=RO_RO4350B1 MLIN ID=TL7 W=1.13179 mm L=18.2827939523261 mm MSUB=RO_RO4350B1 MLIN ID=TL14 W=1.13179 mm L=8.42648946346399 mm MSUB=RO_RO4350B1 MLIN ID=TL20 W=1.13179 mm L=3.44366958458732 mm MSUB=RO_RO4350B1 MLIN ID=TL27 W=1.13179 mm L=6.2 mm MSUB=RO_RO4350B1 MLIN ID=TL28 W=1.13179 mm L=3.9182030314894 mm MSUB=RO_RO4350B1 MOPEN$ ID=TL12 MSUB=RO_RO4350B1 1 2 3 MTEE$ ID=TL15 MSUB=RO_RO4350B1 RES ID=R1 R=6.81 Ohm 1 2 1 2 GPROBE2 ID=GP1 V_METER ID=Vd2 I_METER ID=Id2 12 3 MTEE$ ID=TL13 MSUB=RO_RO4350B1 MLIN ID=TL4 W=W_TLStub mm L=L_TL2Stub mm MSUB=RO_RO4350B1 MLIN ID=TL22 W=1.09377006058279 mm L=1.0929717637931 mm MSUB=RO_RO4350B1 MLIN ID=TL26 W=1.11213944458008 mm L=2.49627311533999 mm MSUB=RO_RO4350B1 MSRSTUB2 ID=ST1 Ro=Ro_stub mm Wg=Wg_stub mm W=W_TLStub mm Theta=Theta_stub Deg MSUB=RO_RO4350B1 1 2 3 MTEE$ ID=TL9 MSUB=RO_RO4350B1 RES ID=R2 R=37.4 Ohm MLIN ID=TL8 W=W_TLStub mm L=L_TL1Stub mm MSUB=RO_RO4350B1 PORT_PS1 P=1 Z=50 Ohm PStart=0 dBm PStop=40 dBm PStep=1 dB PORT1 P=1 Z=50 Ohm Pwr=10 dBm Conn_ViConn_Ii CAP ID=C1 C=47 pF MLIN ID=TL1 W=1.13179 mm L=9.1 mm MSUB=RO_RO4350B1 MLIN ID=TL2 W=1.15424925832038 mm L=8.8091341147881 mm MSUB=RO_RO4350B1 MLIN ID=TL3 W=1.13179 mm L=2.83546915660083 mm MSUB=RO_RO4350B1 MLIN ID=TL5 W=W_DoubleStub mm L=L_DoubleStub mm MSUB=RO_RO4350B1 MLIN ID=TL11 W=W_DoubleStub mm L=L_DoubleStub mm MSUB=RO_RO4350B1 MLIN ID=TL17 W=1.13179 mm L=1.83798534101102 mm MSUB=RO_RO4350B1 MLIN ID=TL19 W=1.13179 mm L=3.27959942836177 mm MSUB=RO_RO4350B1 MLIN ID=TL25 W=1.13179 mm L=2.36734037034666 mm MSUB=RO_RO4350B1 MLIN ID=TL34 W=W_TLStub mm L=L_TL1Stub mm MSUB=RO_RO4350B1 MOPEN$ ID=TL10 MSUB=RO_RO4350B1 MOPEN$ ID=TL18 MSUB=RO_RO4350B1 MOPEN$ ID=TL33 MSUB=RO_RO4350B1 MSRSTUB2 ID=ST3 Ro=Ro_stub mm Wg=Wg_stub mm W=W_TLStub mm Theta=Theta_stub Deg MSUB=RO_RO4350B1 12 3 MTEE$ ID=TL16 MSUB=RO_RO4350B1 1 2 3 MTEE$ ID=TL24 MSUB=RO_RO4350B1 1 2 1 2 GPROBE2 ID=GP2 1 2 3 4 MCROSSX$ ID=MX1 MSUB=RO_RO4350B1 PORT P=2 Z=50 Ohm Input Matching Network Output Matching Network • Some changes were made after using real transmission lines
  • 34. Final design 2. Design 34 • RO4350B substrate with low thickness to take care about termal conductivity 50 2050 4050 6050 8050 10000 Frequency (MHz) Rollet's Condition in Final Design 0 5 10 15 20 0 0.5 1 1.5 2 K (L) B1 (R) 2000 2200 2400 2600 2800 3000 Frequency (MHz) S-Parameters of the PA -35 -30 -25 -20 -15 -10 -5 0 -5 -1.429 2.143 5.714 9.286 12.86 16.43 20 2450MHz 2506 MHz -10 dB 2392 MHz -10 dB 2450 MHz -27.67 dB 2450 MHz 15 dB S11(dB) (L) S21(dB) (R) S12(dB) (L) S22(dB) (L) 0 10 20 30 40 Power (dBm) Comparison 0 5 10 15 20 Gain(dB) 10 20 30 40 50 Pout(dBm) 0 20 40 60 80PAE(%) 26.16dBm 26.16 dBm 40.16 dBm 26.16 dBm 53.3 26.16 dBm 14 dB PAE After PAE Before Pout After (dBm) Pout Before (dBm) Gain(dB) After Gain(dB) Before
  • 35. 2. Design 35 • RO4350B substrate with low thickness to take care about termal conductivity Final design RF OUTRF IN
  • 36. Outline 1. Introduction 2. Design 3. Manufacturing 4. Results 5. Conclusions and Future work
  • 37. Heat Sink Selection 3. Manufacturing 37 𝜃𝑗𝑎 = 𝜃𝑗𝑐 + 𝜃𝑐𝑠 + 𝜃𝑠𝑎 = 𝑇𝑗 − 𝑇𝑎 𝑄 = 14.8192 º𝐶/𝑊 𝜃𝑐𝑠 = 𝜌 · 𝑡 𝐴 = 0.5 º𝐶/𝑊 (𝑇𝑦𝑝. 𝑖𝑛 𝑡ℎ𝑒𝑟𝑚𝑎𝑙 𝑐𝑜𝑚𝑝𝑜𝑢𝑛𝑑) 𝜃𝑠𝑎 = 𝑇𝑗 − 𝑇𝑎 𝑄 − (𝜃jc + 𝜃𝑐𝑠) 𝜃𝑗𝑐 = 8.0 º𝐶/𝑊 (𝑇𝑟𝑎𝑛𝑠𝑖𝑠𝑡𝑜𝑟 𝐷𝑎𝑡𝑎𝑠ℎ𝑒𝑒𝑡) 𝜃𝑠𝑎𝑀𝑎𝑥 = 6.31921 º 𝐶 𝑊
  • 38. Heat Sink Selection 3. Manufacturing 38 𝜃 )𝑠𝑎 (641𝑘 ≃ 2.43 º 𝐶 𝑊
  • 41. Outline 1. Introduction 2. Design 3. Manufacturing 4. Results 5. Conclusions and Future work
  • 43. 4. Results 43 • To correct the frequency shift: 𝑅𝑒𝑠𝑖𝑧𝑒 𝑓𝑎𝑐𝑡𝑜𝑟 = 𝑓𝑠ℎ𝑖𝑓𝑡𝑒𝑑 𝑓0 = 2200 2450 = 44 49 ≃ 0.898
  • 44. 4. Results Inconvenients and unexpected stuff After 4 minutes working, the transistor was BURNT! Potential causes: a. Thermal compound b. Q-Point too close to the maximum dissipation curve c. Testing with LOW Input Power. LOW PAE. HIGH dissipation d. When frequency shift occurs, at 2.45GHz we have a totally different behaviour • IT HAS NOT BEEN POSSIBLE TO MEASURE ANYMORE 44
  • 45. Outline 1. Introduction 2. Design 3. Manufacturing 4. Results 5. Conclusions and Future work
  • 46. Conclusions • Initial thermal analysis is critical • Project with high didactic potential Future Work • Fix the overheating issue • Design other amplifier classes such as AB and B to be able to compare its performance, efficiency and so forth 5. Conclusions and Future Work 46