VTU 4TH SEM CSE COMPUTER ORGANIZATION SOLVED PAPERS OF JUNE-2013 JUNE-2014 & JUNE-2015

For Solved Question Papers of UGC-NET/GATE/SET/PGCET in Computer Science, visit http://victory4sure.weebly.com/
VTU
N
O
TESBYSR
I

COMPUTER ORGANIZATION SOLVED PAPER JUNE- 2013
1
1 a. With a diagram, discuss basic operational concepts of a computer. (06 Marks)
Ans:
BASIC OPERATIONAL CONCEPTS
• The processor contains ALU, control-circuitry and many registers (Figure: 1.2).
• The IR(Instruction-Register) holds the instruction that is currently being executed.
• The PC(Program Counter) contains the memory-address of the next-instruction to be
fetched & executed.
• The processor also contains ‘n’ general-purpose registers R0 through Rn-1.
• The MAR(Memory Address Register) holds the address of the memory-location to be
accessed.
• The MDR(Memory Data Register) contains the data to be written into or read out of the
addressed location.
Following are the steps that take place to execute an instruction
• The address of first instruction (to be executed) gets loaded into PC.
• The contents of PC(i.e. address) are transferred to the MAR & control-unit issues Read signal
to memory.
• After certain amount of elapsed time, the first instruction is read out of memory and placed
into MDR.
• Next, the contents of MDR are transferred to IR. At this point, the instruction can be decoded
& executed.
• To fetch an operand, it's address is placed into MAR & control-unit issues Read signal.
• Then, operand is transferred from memory into MDR, and then it is transferred from MDR to
ALU.
• Likewise required number of operands is fetched into processor.
• Finally, ALU performs the desired operation.
• If the result is to be stored in the memory, then the result is sent to the MDR.
• The address of the location where the result is to be stored is sent to the MAR and a Write
cycle is initiated.
• At some point, contents of PC are incremented to point to next instruction in the program.
VTU
N
O
TESBYSR
I

2
1 b. List the different systems used to represent a signed number and give one
example for each. Specify which number representation system is preferred in a
computer and why? (04 Marks)
Ans:
NUMBER REPRESENTATION
• Numbers can be represented in 3 formats:
1) Sign and magnitude
2) 1's complement
3) 2's complement
• In all three formats, MSB=0 for +ve numbers & MSB=1 for -ve numbers.
• In the sign-and-magnitude system, negative value is obtained by changing the MSB from
0 to 1 of the corresponding positive value. For example, +5 is represented by 0101 &
-5 is represented by 1101.
• In 1's complement representation, negative values are obtained by complementing each
bit of the corresponding positive number. For example, -3 is obtained by complementing each
bit in 0011 to yield 1100. (In other words, the operation of forming the 1's complement of a
given number is equivalent to subtracting that number from 2n
-1).
• In the 2's complement system, forming the 2's complement of a number is done by
subtracting that number from 2n
.
(In other words, the 2's complement of a number is obtained by adding 1 to the 1's
complement of that number).
• The 2's complement representation system is preferred in a computer because it yields the
most efficient way to carry out addition and subtraction operations.
1 c. Perform following operations on the 5-bit signed numbers using 2's complement
representation system. Also indicate whether overflow has occurred. (10 Marks)
i) (-10)+(-13) ii)(-10)-(+4) iii)(-3)+(-8) iv) (-10)-(+7)
Ans:
Solution:
VTU
N
O
TESBYSR
I

3
2 a. Define addressing mode. Explain the following addressing modes with an
example for each: (10 Marks)
i) index addressing ii) indirect addressing mode
iii) relatve addressing mode iv) auto decrement addressing mode
Ans:
ADDRESSING MODES
• The different ways in which the location of an operand is specified in an instruction are
referred to as addressing modes (Table 2.1).
i) Index Mode
• The operation is indicated as X(Ri)
where X=the constant value contained in the instruction
Ri=the name of the index register
• The effective-address of the operand is given by EA=X+[Ri]
• The contents of the index-register are not changed in the process of generating the
effective-address (Figure: 2.14).
• In an assembly language program, the constant X may be given either
→ as an explicit number or
→ as a symbolic-name representing a numerical value.
ii) Indirect Mode
• The EA of the operand is the contents of a register(or memory-location) whose address
appears in the instruction.
• The register (or memory-location) that contains the address of an operand is called a
pointer. {The indirection is denoted by ( ) sign around the register or memory-location}.
E.g: Add (R1),R0 ;The operand is in memory. Register R1 gives the effective-
;address(B) of the operand. The data is read from location B and
;added to contents of register R0
VTU
N
O
TESBYSR
I

4
iii) Relative Mode
• This is similar to index-mode with an exception: The effective address is determined using
the PC in place of the general purpose register Ri.
• The operation is indicated as X(PC).
• X(PC) denotes an effective-address of the operand which is X locations above or below the
current contents of PC.
• Since the addressed-location is identified "relative" to the PC, the name Relative mode is
associated with this type of addressing.
• This mode is used commonly in conditional branch instructions.
• An instruction such as
Branch > 0 LOOP ;Causes program execution to go to the branch target location
;identified by name LOOP if branch condition is satisfied.
iv) Auto Decrement Mode
• The contents of a register specified in the instruction are first automatically decremented and
are then used as the effective address of the operand.
• This mode is denoted as
-(Ri) ;where Ri=pointer register
• These 2 modes can be used together to implement an important data structure called a
stack.
2 b. With a neat block diagram, describe the input and output operations. (05
Marks)
Ans:
BASIC INPUT/OUTPUT OPERATIONS
• Consider the problem of moving a character-code from the keyboard to the processor.
For this transfer, buffer-register(DATAIN) & a status control flags(SIN) are used.
• Striking a key stores the corresponding character-code in an 8-bit buffer-register(DATAIN)
associated with the keyboard (Figure: 2.19).
• To inform the processor that a valid character is in DATAIN, a SIN is set to 1.
• A program monitors SIN, and when SIN is set to 1, the processor reads the contents of
DATAIN.
• When the character is transferred to the processor, SIN is automatically cleared to 0.
• If a second character is entered at the keyboard, SIN is again set to 1 and the process
repeats.
• An analogous process takes place when characters are transferred from the processor to the
display. A buffer-register, DATAOUT, and a status control flag, SOUT are used for this transfer.
• When SOUT=1, the display is ready to receive a character.
• The transfer of a character to DATAOUT clears SOUT to 0.
• The buffer registers DATAIN and DATAOUT and the status flags SIN and SOUT are part of
circuitry commonly known as a device interface.
VTU
N
O
TESBYSR
I

5
2 c. Discuss briefly encoding of machine instructions. (05 Marks)
Ans:
ENCODING OF MACHINE INSTRUCTIONS
• To be executed in a processor, an instruction must be encoded in a binary-pattern. Such
encoded instructions are referred to as machine instructions.
• The instructions that use symbolic names and acronyms are called assembly language
instructions.
• We have seen instructions that perform operations such as add, subtract, move, shift,
rotate, and branch. These instructions may use operands of different sizes, such as 32-bit and
8-bit numbers.
• Let us examine some typical cases.
The instruction
Add R1, R2 ;Has to specify the registers R1 and R2, in addition to the OP code. If the
;processor has 16 registers, then four bits are needed to identify each
;register. Additional bits are needed to indicate that the Register
;addressing-mode is used for each operand.
• OP code for given instruction refers to type of operation that is to be performed (Fig: 2.39).
• Source and destination field refers to source and destination operand respectively.
• The "Other info" field allows us to specify the additional information that may be needed
such as an index value or an immediate operand.
VTU
N
O
TESBYSR
I

6
3 a. With neat sketches, explain various methods for handling multiple interrupt
requests. (12 Marks)
Ans:
i) Polling
• Information needed to determine whether a device is requesting an interrupt is available in
its status-register.
• When a device raises an interrupt-request, it sets IRQ bit to 1 in its status-register (Fig 4.3).
• KIRQ and DIRQ are the interrupt-request bits for keyboard & display.
• Simplest way to identify interrupting device is to have ISR poll all I/O devices connected to
bus.
• The first device encountered with its IRQ bit set is the device that should be serviced. After
servicing this device, next requests may be serviced.
• Main advantage: Simple & easy to implement.
Main disadvantage: More time spent polling IRQ bits of all devices (that may not be
requesting any service).
ii) Vectored Interrupts
• A device requesting an interrupt identifies itself by sending a special-code to processor over
bus. (This enables processor to identify individual devices even if they share a single interrupt-
request line).
• The code represents starting-address of ISR for that device.
• ISR for a given device must always start at same location.
• The address stored at the location pointed to by interrupting-device is called the interrupt-
vector.
• Processor
→ loads interrupt-vector into PC &
→ executes appropriate ISR
• Interrupting-device must wait to put data on bus only when processor is ready to receive it.
• When processor is ready to receive interrupt-vector code, it activates INTA line.
• I/O device responds by sending its interrupt-vector code & turning off the INTR signal.
VTU
N
O
TESBYSR
I

7
3 b. Define bus arbitration. Explain any one approach of bus arbitration. (08 Marks)
Ans:
• Bus arbitration is the process by which next device to become the bus-master is selected
and bus-mastership is transferred to it.
• There are 2 approaches to bus arbitration:
1) Centralized arbitration: A single bus-arbiter performs the required arbitration.
2) Distributed arbitration: All devices participate in selection of next bus-master.
CENTRALIZED ARBITRATION
• A single bus-arbiter performs the required arbitration (Figure: 4.20 & 4.21).
• Normally, processor is the bus-master unless it grants bus-mastership to one of the DMA
controllers.
• A DMA controller indicates that it needs to become bus-master by activating BR (Bus-
Request line).
• The signal on the BR line is the logical OR of bus-requests from all devices connected to it.
• When BR is activated, processor activates Bus-Grant signal(BG1) indicating to DMA
controllers that they may use bus when it becomes free. (This signal is connected to all DMA
controllers using a daisy-chain arrangement).
• If DMA controller-1 is requesting the bus, it blocks propagation of grant-signal to other
devices.
Otherwise, it passes the grant downstream by asserting BG2.
• Current bus-master indicates to all devices that it is using bus by activating BBSY (Bus-Busy
line).
• Arbiter circuit ensures that only one request is granted at any given time according to a
predefined priority scheme
VTU
N
O
TESBYSR
I

8
DISTRIBUTED ARBITRATION
• All device participate in the selection of next bus-master (Figure 4.22)
• Each device on bus is assigned a 4-bit identification number (ID).
• When 1 or more devices request bus, they
→ assert Start-Arbitration signal &
→ place their 4-bit ID numbers on four open-collector lines 0BRA through 3BRA .
• A winner is selected as a result of interaction among signals transmitted over these lines by
all contenders.
• Net outcome is that the code on 4 lines represents request that has the highest ID number.
• Advantage: This approach offers higher reliability since operation of bus is not dependent
on any single device.
VTU
N
O
TESBYSR
I

9
4 a. With a neat diagram, explain in detail the input interface circuit. (10 Marks)
Ans:
Input Interface Circuit
Figure 4.29: Input Interface Circuit
• Output lines of DATAIN are connected to the data lines of the bus by means of 3 state
drivers (Figure 4.29).
• Drivers are turned on when the processor issues a read signal and the address selects this
register. SIN signal is generated using a status flag circuit.
• It is connected to line D0of the processor bus using a three‐state driver.
• Address decoder selects the input interface based on bits A1 through A31.
• Bit A0 determines whether the status or data register is to be read, when Master‐ready is
active.
• In response, the processor activates the Slave‐ready signal, when either the Read‐status or
Read‐data is equal to 1, which depends on line A0.
VTU
N
O
TESBYSR
I

10
4 b. List out the functions of an I/O interface. (03 Marks)
Ans:
• I/O Interfaces provide a way to interact with computer hardware.
• The interface of each device is capable of encoding and decoding the I/O signals in an
understandable form for both input and output devices.
4 c. Discuss briefly the protocols of universal serial bus. (07 Marks)
Ans:
USB PROTOCOLS
• All information transferred over the USB is organized in packets, where a packet consists of
one or more bytes of information.
• The information transferred on the USB can be divided into two broad categories: control
and data (Figure: 4.45).
• Control packets perform such tasks as addressing a device to initiate data transfer,
acknowledging that data have been received correctly, or indicating an error.
• Data packets carry information that is delivered to a device.
• A packet consists of one or more fields containing different kinds of information. The first
field of any packet is called the packet identifier, PID, which identifies the type of that packet.
• They are transmitted twice. The first time they are sent with their true values, and the
second time with each bit complemented
• The four PID bits identify one of 16 different packet types. Some control packets, such as
ACK (Acknowledge), consist only of the PID byte.
• Control packets used for controlling data transfer operations are called token packets
VTU
N
O
TESBYSR
I

11
5 a. Briefly explain any two cache mapping functions.(06 Marks)
Ans:
DIRECT MAPPING
• It is the simplest technique in which block j of the main memory maps onto block “j‟ modulo
128 of the cache.
• Thus whenever one of the main memory blocks 0, 128, 256 is loaded in the cache, it is
stored in block 0.
• Block 1, 129, 257 are stored in cache block 1 and so on.
• The contention may arise when,
→ When the cache is full
→ When more than one memory block is mapped onto a given cache block position.
• The contention is resolved by allowing the new blocks to overwrite the currently resident
block.
• Placement of block in the cache is determined from memory address.
• The memory address is divided into 3 fields (Figure: 5.15). They are,
1) Low Order 4 bit field(word): Selects one of 16 words in a block.
2) 7 bit cache block field: When new block enters cache, 7 bit determines the cache
position in which this block must be stored.
3) 5 bit Tag field: The high order 5 bits of the memory address of the block is
stored in 5 tag bits associated with its location in the cache.
• As execution proceeds, the high order 5 bits of the address are compared with tag bits
associated with that cache location.
• If they match, then the desired word is in that block of the cache.
• If there is no match, then the block containing the required word must be first read from the
main memory and loaded into the cache.
VTU
N
O
TESBYSR
I

12
ASSOCIATIVE MAPPING
• The main memory block can be placed into any cache block position (Figure: 5.16).
• 12 tag bits will identify a memory block when it is resolved in the cache.
• The tag bits of an address received from the processor are compared to the tag bits of each
block of the cache to see if the desired block is present. This is called associative mapping.
• It gives complete freedom in choosing the cache location.
• A new block that has to be brought into the cache has to replace(eject) an existing block if
the cache is full.
• The memory has to determine whether a given block is in the cache.
• A search of this kind is called an associative Search.
Advantage
• It is more flexible than direct mapping technique.
Disadvantage
• Its cost is high.
VTU
N
O
TESBYSR
I

13
5 b. With a neat diagram, explain the translation of a virtual address to a physical
address. (08 Marks)
Ans:
VIRTUAL ADDRESS
• Techniques that automatically move program and data blocks into the physical main memory
when they are required for execution is called the Virtual Memory.
Virtual to Physical Address Translation
• All programs and data are composed of fixed length units called Pages (Figure: 5.27).
• The Page consists of a block of words that occupy contiguous locations in the main memory.
• The pages are commonly range from 2K to 16K bytes in length.
• The cache bridge speed up the gap between main memory and secondary storage and it is
implemented in software techniques.
• Each virtual address generated by the processor contains virtual Page number (Low order
bit) and offset(High order bit)
• Virtual Page number+Offset → Specifies the location of a particular byte (or word) within a
page.
• Page Table: It contains the information about the main memory address where the page is
stored & the current status of the page.
• Page Frame: An area in the main memory that holds one page is called the page frame.
• Page Table Base Register: It contains the starting address of the page table.
• Virtual Page Number + Page Table Base register → Gives the address of the
corresponding entry in the page table. I.e. it gives the starting address of the page if that
page currently resides in memory.
• Control Bits in Page Table: The Control bits specifies the status of the page while it is in
main memory.
• Function of Control Bits: The control bit indicates the validity of the page i.e. it checks
whether the page is actually loaded in the main memory.
VTU
N
O
TESBYSR
I

14
5 c. Discuss in detail any one feature of memory design that leads to improved
performance of computer. (06 Marks)
Ans:
MEMORY INTERLEAVING
• If the main memory of a computer is structured as a collection of physically separate
modules, each with its own address buffer register (ABR) and data buffer register (DBR),
memory access operations may proceed in more than one module at the same time.
• Thus, the aggregate rate of transmission of words to and from the main memory system can
be increased.
• The low-order k bits of the memory address select a module, and the high-order m bits
name a location within that module (Figure: 5.25).
• In this way, consecutive addresses are located in successive modules.
• Thus, any component of the system that generates requests for access to consecutive
memory locations can keep several modules busy at any one time. T
• This results in both faster accesses to a block of data and higher average utilization of the
memory system as a whole.
• To implement the interleaved structure, there must be 2k modules; otherwise, there will be
gaps of nonexistent locations in the memory address space.
6 a. Perform signed multiplication of numbers (-12) and (-11) using Booth’s
algorithm. (08 Marks)
Ans:
Solution:
VTU
N
O
TESBYSR
I

15
6 b. Given A=10101 and B=00100, perform A/B using restoring division
algorithm.(08 Marks)
Ans:
• Procedure: Do the following n times
1) Shift A and Q left one binary position.
2) Subtract M from A, and place the answer back in A
3) If the sign of A is 1, set q0 to 0 and add M back to A(restore A).
If the sign of A is 0, set q0 to 1 and no restoring done.
VTU
N
O
TESBYSR
I

16
6 c. Design a logic circuit to perform addition/subtraction of two ‘n’ numbers X and
Y. (04 Marks)
Ans:
• The n-bit adder can be used to add 2's complement numbers X and Y (Figure 6.3).
• Overflow can only occur when the signs of the 2 operands are the same.
• In order to perform the subtraction operation X-Y on 2's complement numbers X and Y; we
form the 2's
complement of Y and add it to X.
• Addition or subtraction operation is done based on value applied to the Add/Sub input
control-line.
• Control-line=0 for addition, applying the Y vector unchanged to one of the adder inputs.
Control-line=1 for subtraction, the Y vector is 2's complemented.
7 a. Write down the control sequence for the instruction Add R4,R5,R6 for three- bus
organization. (04 Marks)
Ans:
• Control sequence for the instruction Add R4,R5,R6 is as follows
1) PCout, R=B, MARin, Read, IncPC
2) WMFC
3) MDRout, R=B, IRin
4) R4outA, R5outB, SelectA, Add, R6in, End
VTU
N
O
TESBYSR
I

17
7 b. With a neat sketch, explain the organization of a micro programmed control unit
(08 Marks)
Ans:
MICROPROGRAMMED CONTROL
• Control-signals are generated by a program (Figure: 7.15).
• CW (Control word) is a word whose individual bits represent various control-signals (like
Add, End, Zin). {Each of the control-steps in control sequence of an instruction defines a
unique combination of 1s & 0s in the CW}.
• Individual control-words in microroutine are referred to as microinstructions(Figure: 7.16).
• A sequence of CWs corresponding to control-sequence of a machine instruction constitutes
the microroutine.
• The microroutines for all instructions in the instruction-set of a computer are stored in a
special memory called the CS (control store).
• Control-unit generates control-signals for any instruction by sequentially reading CWs of
corresponding microroutine from CS.
• µPC (Microprogram counter) is used to read CWs sequentially from CS.
• Every time a new instruction is loaded into IR, output of "starting address generator" is
loaded into µPC.
• Then, µPC is automatically incremented by clock,
causing successive microinstructions to be read from CS.
Hence, control-signals are delivered to various parts of processor in correct sequence.
VTU
N
O
TESBYSR
I

18
7 c. With an example, explain the field coded microinstructions. (08 Marks)
Ans:
MICROINSTRUCTIONS
• Drawbacks of microprogrammed control:
1) Assigning individual bits to each control-signal results in long microinstructions.
2) Available bit-space is poorly used.
• Solution: Signals can be grouped because
1) Most signals are not needed simultaneously. E.g. only one function of ALU
can be activated at a time.
2) Many signals are mutually exclusive. E.g. Read and Write signals to the
memory cannot be activated simultaneously.
• Grouping control-signals into fields requires a little more hardware because decoding-circuits
must be used to decode bit patterns of each field into individual control signals (Figure: 7.19).
• Advantage: This method results in a smaller control-store (only 20 bits are needed to store
the patterns for the 42 signals).
• Techniques of grouping of control signals:
1) Vertical organization and
2) Horizontal organization.
Vertical Organization Horizontal Organization
Highly encoded schemes that use compact
codes to specify only a small number of
control functions in each microinstruction are
referred to as a vertical organization
The minimally encoded scheme in which many
resources can be controlled with a single
microinstuction is called a horizontal
organization
Slower operating speeds Useful when higher operating speed is desired
Short formats Long formats
Limited ability to express parallel
microoperations
Ability to express a high degree of parallelism
Considerable encoding of the control
information
Little encoding of the control information
Microinstruction
VTU
N
O
TESBYSR
I

19
8 a. Describe the working of message passing multicomputer(MPM) architecture. (08
Marks)
Ans:
MESSAGE-PASSING MULTIPROCESSORS (CLUSTER)
• Communicating between multiple processors by explicitly sending and receiving information.
1) Send message routine: A routine used by a processor in machines with private
memories to pass to another processor.
2) Receive message routine: A routine used by a processor in machines with private
memories to accept a message from another processor.
• Each processor has it’s own private physical address space (Figure: 7.4).
• Provided the system has routines to send and receive messages, coordination is built in with
message passing, since one processor knows when a message is sent, and the receiving
processor knows when a message arrives.
• If the sender needs confirmation that the message has arrived, the receiving processor can
then send an acknowledgment message back to the sender.
• Clusters: Collections of computers connected via I/O over standard network switches to
form a message- passing multiprocessor.
• Each runs a distinct copy of the operating system.
• Virtually every Internet service relies on clusters of commodity servers and switches.
• Disadvantages of cluster:
→ Expensive: The cost of administering a cluster of n machines is about the same as
the cost of administering n independent machines.
→ The processors in a cluster are usually connected using the I/O interconnect of each
computer. The I/O interconnect has lower bandwidth and higher latency.
→ The overhead in the division of memory.
VTU
N
O
TESBYSR
I

20
8 b. Briefly explain any two parallel computer architecture. (08 Marks)
Ans:
• Two types of parallel computers are:
1) Multiprocessors
2) Multicomputers
MULTIPROCESSORS (SHARED MULTIPROCESSORS)
• A parallel processor with a single address space, implying implicit communication with loads
and stores(Figure: 7.2).
• Processors communicate through shared variables in memory, with all processors capable of
accessing any memory location via loads and stores.
• Two most common shared memory multiprocessors models are 1) UMA & 2) NUMA.
1) Uniform Memory Access (UMA): A multiprocessor in which accesses to main
memory take about the same amount of time no matter which processor requests the
access and no matter which word is asked.
2) Non Uniform Memory Access (NUMA): A type of single address space
multiprocessor in which some memory accesses are much faster than others depending
on which processor asks for which word.
• To provide synchronization, a lock is used. Only one processor at a time can acquire the
lock, and other processors interested in shared data must wait until the original processor
unlocks the variable.
MULTICOMPUTERS
• A conventional uniprocessor has a single instruction stream and single data stream, and a
conventional multiprocessor has multiple instruction streams and multiple data streams. These
two categories are abbreviated SISD and MIMD, respectively.
• SIMD computers operate on vectors of data.
• All the parallel execution units are synchronized and they all respond to a single instruction
that emanates from a single program counter (PC).
• Each execution unit has its own address registers, and so each unit can have different data
addresses.
• Advantage: reduced size of program memory.
• Two most common Multicomputers models are 1) SIMD in x86 & 2) Vector architectures
1) SIMD in x86: Multimedia Extensions
• The most widely used variation of SIMD is found in almost every microprocessor
today, and is the basis of the hundreds of MMX and SSE instructions of the x86
microprocessor.
• They were added to improve performance of multimedia programs.
• These instructions allow the hardware to have many ALUs operate simultaneously or,
equivalently, to partition a single, wide ALU into many parallel smaller ALUs that
operate simultaneously.
2) Vector Architectures
• An older and more elegant interpretation of SIMD is called a vector architecture.
• The vector architectures pipelined the ALU to get good performance at lower cost.
• The basic philosophy of vector architecture is to collect data elements from memory,
put them in order into a large set of registers, operate on them sequentially in
registers, and then write the results back to memory.
• A key feature of vector architectures is a set of vector registers.
VTU
N
O
TESBYSR
I

21
8 c. List out any four differences between shared multiprocessor and cluster. (04
Marks)
Ans:
Message-Passing Multiprocessors
(Cluster)
Shared Multiprocessor
Each processor has its own private physical
address space.
A single physical address space is shared by all
processors.
More Expensive: The cost of administering a
cluster of n machines is about the same as
the cost of administering n independent
machines.
Less Expensive: The cost of administering a
shared memory multiprocessor with n processors
is about the same as administering a single
machine.
The processors in a cluster are usually
connected using the I/O interconnect of each
computer. The I/0 interconnect has lower
bandwidth and higher latency.
The cores in a multiprocessor are usually
connected on the memory interconnect of the
computer. The memory interconnect has higher
bandwidth and lower latency, allowing much
better communication performance.
The division of memory: a cluster of n
machines has n independent memories and
n copies of the operating system.
A shared memory multiprocessor allows a single
program to use almost all the memory in the
computer, and it only needs a single copy of the
OS.
VTU
N
O
TESBYSR
I

1
1 (a) Draw the connection between processor and memory and mention the
functions of each component in the connection. (8 Marks)
Ans: For answer, refer Solved Paper June-2013 Q.No.1a
1 (b) Write the difference between RISC and CISC processors. (4 Marks)
Ans:
1 (c) A program contain 1000 instruction Out of that 25% instructions requires 4
clock cycles. 40% instructions requires 5 clock and remaining 3 clock cycles for
execution. Find the total time required to execute the program running in a 1GHz
machine. (5 Marks)
Ans:
Solution:
N=1000
25% of N= 250 instructions require 4 clock cycles,
40% of N =400 instructions require 5 clock cycles,
35% of N=350 instructions require 3 clock cycles
T = (N*S)/R = 250*4+400*5+350*3/1*109
=1000+2000+1050/1*109
= 4.05 µs
1 (d) Add +5 and -9 2's compliment method.(3 Marks)
Ans:
Solution:
00101 (+5)
+10111 (-9)
---------------
11100 (-4)
2 (a) Explain i) indirect addressing mode
ii) indexed addressing mode and
iii) immediate addressing mode. (8 Marks)
Ans: i) For answer, refer Solved Paper June-2013 Q.No.2a
Ans: ii) For answer, refer Solved Paper June-2013 Q.No.2a
Ans: iii) Immediate Mode
• The operand is given explicitly in the instruction.
• For example, the instruction,
Move #200, R0 ;Place the value 200 in register R0
• Clearly, the immediate mode is only used to specify the value of a source-operand.
VTU
N
O
TESBYSR
I

2
2 (b) Explain different rotate instructions. (6 Marks)
Ans:
ROTATE OPERATIONS
• In shift operations, the bits shifted out of the operand are lost, except for the last bit shifted
out which is retained in the Carry-flag C (Figure: 2.32).
• To preserve all bits, a set of rotate instructions can be used.
• They move the bits that are shifted out of one end of the operand back into the other end.
• Two versions of both the left and right rotate instructions are usually provided.
In one version, the bits of the operand are simply rotated.
In the other version, the rotation includes the C flag.
VTU
N
O
TESBYSR
I

3
2 (c) Write ALP program to copy 'N' numbers from array 'A' to array 'B' using direct
addresses. (Assume A and B are the starting memory locations of a array).(6 Marks)
Ans:
Program:
Move N, R1 ; initialize counter R1=N
Move #A, R2 ; R2 is used as a pointer to the numbers in the list A
Move #B, R3 ; R3 is used as a pointer to the numbers in the list B
Clear R0 ; set sum R0=0
LOOP Move (R2), R0 ; move data pointed by R2 into R0 register
Move R0, (R3) ; move R0 content to memory pointed by R3
Decrement R1 ; decrement counter R1
Branch > 0 LOOP ; repeat until counter R1 becomes 0
3 (a) Explain the following terms:
i) Interrupt service routine
ii) Interrupt latency
iii) Interrupt disabling. (6 Marks)
Ans: i)
• The routine executed in response to an interrupt-request is called ISR(Interrupt Service
Routine).
Ans: ii)
• Interrupt latency is the time that elapses from when an interrupt is generated to when the
source of the interrupt is serviced.
Ans: iii)
DISABLING INTERRUPTS
• To prevent the system from entering into an infinite-loop because of interrupt, there are 3
possibilities:
1) Have the processor-hardware ignore the interrupt-request line until the execution of
the first instruction of the ISR has been completed.
2) Have the processor automatically disable interrupts before starting the execution of
the ISR.
3) The processor has a special interrupt-request line for which the interrupt-handling
circuit responds only to the leading edge of the signal. Such a line is said to be edge-
triggered
3 (b) With a diagram, explain daisy chaining technique. (6 Marks)
Ans:
DAISY CHAINING INTERUPT SCHEME
• INTR line is common to all devices (Figure: 4.8).
• INTA line is connected in a daisy-chain fashion such that INTA signal propagates serially
through devices.
• When several devices raise an interrupt-request and INTR line is activated, processor
responds by setting INTA line to 1. This signal is received by device 1.
• Device 1 passes signal on to device 2 only if it does not require any service.
• If device 1 has a pending-request for interrupt, it blocks INTA signal and proceeds to put its
identifying code on data lines.
• Device that is electrically closest to processor has highest priority.
• Main advantage: This allows the processor to accept interrupt-requests from some devices
but not from others depending upon their priorities.
Figure: 4.31: daisy chaining technique
VTU
N
O
TESBYSR
I

4
3 (c) What you mean by bus arbitration? Briefly explain different bus arbitration
techniques. (8 Marks)
Ans: For answer, refer Solved Paper June-2013 Q.No.3b
4 (a) With a block diagram, explain how printer is interfaced to processor.(8 Marks)
Ans:
• Keyboard is connected to a processor using a parallel port (Figure: 4.31).
• Processor is 32‐bits and uses memory‐mapped I/O and the asynchronous bus protocol.
• On the processor side of the interface we have:
→ Data lines.
→ Address lines
→ Control or R/W line.
‐> Master‐ready signal and
→ Slave‐ready signal.
• On the keyboard side of the interface:
→ Encoder circuit which generates a code for the key pressed.
→ Debouncing circuit which eliminates the effect of a key bounce (a single key stroke
may appear as multiple events to a processor).
→ Data lines contain the code for the key.
→ Valid line changes from 0 to 1 when the key is pressed. This causes the code to
be loaded into DATAIN and SIN to be set to 1.
VTU
N
O
TESBYSR
I

5
4 (b) Explain the architecture and addressing scheme of USB.(8 Marks)
Ans:
USB ARCHITECTURE
• To accommodate a large number of devices that can be added or removed at any time, the
USB has the tree structure as shown in the figure 4.43.
• Each node of the tree has a device called a hub, which acts as an intermediate control point
between the host and the I/O devices.
• At the root of the tree, a root hub connects the entire tree to the host computer.
• The leaves of the tree are the I/O devices being served (for example, keyboard or speaker).
• In normal operation, a hub copies a message that it receives from its upstream connection
to all its downstream ports.
• As a result, a message sent by the host computer is broadcast to all I/O devices, but only
the addressed device will respond to that message.
USB ADDRESSING
• Each device on the USB, whether it is a hub or an I/O device, is assigned a 7‐bit address.
• This address is local to the USB tree and is not related in any way to the addresses used on
the processor bus.
• A hub may have any number of devices or other hubs connected to it, and addresses are
assigned arbitrarily.
• When a device is first connected to a hub, or when it is powered on, it has the address 0.
• The hardware of the hub to which this device is connected is capable of detecting that the
device has been connected, and it records this fact as part of its own status information.
• Periodically, the host polls each hub to collect status information and learn about new
devices that may have been added or disconnected.
• When the host is informed that a new device has been connected, it uses a sequence of
commands to send a reset signal on the corresponding hub port, read information from the
device about its capabilities, send configuration information to the device, and assign the
device a unique USB address.
• Once this sequence is completed, the device begins normal operation and responds only to
the new address.
VTU
N
O
TESBYSR
I

6
4 (c) Define two types of SCSI controller.(4 Marks)
Ans:
• The controller connected to SCSI bus is of 2 types. They are
i) Initiator
ii) Target
i) Initiator
• It has the ability to select a particular target & to send commands specifying the operation to
be performed.
• They are the controllers on the processor side.
ii) Target
• The disk controller operates as a target.
• It carries out the commands it receive from the initiator.
• The initiator establishes a logical connection with the intended target.
5 (a) Explain direct memory mapping technique. (6 Marks)
5 (b) What is virtual memory? With a diagram, explain how virtual memory address
is translated. (8 Marks)
VTU
N
O
TESBYSR
I

7
5 (c) Explain the working of 16 megabyte DRAM chip configured as 1M×16 memory
chip. (6 Marks)
Ans:
• The 4 bit cells in each row are divided into 512 groups of 8 (Figure: 5.7).
• 21 bit address is needed to access a byte in the memory(12 bit→To select a row,9
bit→Specify the group of 8 bits in the selected row).
A8-0 → Row address of a byte.
A20-9 → Column address of a byte.
• During Read/ Write operation,the row address is applied first. It is loaded into the row
address latch in response to a signal pulse on Row Address Strobe(RAS) input of the chip.
• During Read/ Write operation , the row address is applied first. It is loaded into the row
address latch in response to a signal pulse on Row Address Strobe(RAS) input of the chip.
• When a Read operation is initiated, all cells on the selected row are read and refreshed.
• Shortly after the row address is loaded,the column address is applied to the address pins &
loaded into Column Address Strobe(CAS).
• The information in this latch is decoded and the appropriate group of 8 Sense/Write circuits
are selected.
• R/W =1(read operation)→The output values of the selected circuits are transferred to the
data lines D0 - D7.
• R/W =0(write operation)→The information on D0 - D7 are transferred to the selected
circuits.
• RAS and CAS are active low so that they cause the latching of address when they change
from high to low. This is because they are indicated by RAS & CAS.
• To ensure that the contents of a DRAM „s are maintained, each row of cells must be
accessed periodically.
• Refresh operation usually perform this function automatically.
• A specialized memory controller circuit provides the necessary control signals RAS & CAS,
that govern the timing.
• The processor must take into account the delay in the response of the memory. Such
memories are referred to as Asynchronous DRAM’s.
VTU
N
O
TESBYSR
I

8
6 (a) Design 4 bit carry look ahead logic and explain how it is faster them 4 bit ripple
adder.(8 Marks)
Ans:
CARRY-LOOKAHEAD ADDITIONS
• The logic expression for si(sum) and ci+1(carry-out) of stage i are
si=xi+yi+ci ------(1) ci+1=xiyi+xici+yici ------(2)
• Factoring (2) into
ci+1=xiyi+(xi+yi)ci
we can write
ci+1=Gi+PiCi where Gi=xiyi and Pi=xi+yi
• The expressions Gi and Pi are called generate and propagate functions (Figure 6.4).
• If Gi=1, then ci+1=1, independent of the input carry ci. This occurs when both xi and yi are 1.
Propagate function means that an input-carry will produce an output-carry when either xi=1
or yi=1.
• All Gi and Pi functions can be formed independently and in parallel in one logic-gate delay.
• Expanding ci terms of i-1 subscripted variables and substituting into the ci+1 expression, we
obtain
ci+1=Gi+PiGi-1+PiPi-1Gi-2. . . . . .+P1G0+PiPi-1 . . . P0c0
• Conclusion: Delay through the adder is 3 gate delays for all carry-bits &
4 gate delays for all sum-bits.
• Consider the design of a 4-bit adder. The carries can be implemented as
c1=G0+P0c0
c2=G1+P1G0+P1P0c0
c3=G2+P2G1+P2P1G0+P2P1P0c0
c4=G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0c0
• The carries are implemented in the block labeled carry-lookahead logic. An adder
implemented in this form is called a carry-lookahead adder (Figure: 6.4).
• Limitation: If we try to extend the carry-lookahead adder for longer operands, we run into a
problem of gate fan-in constraints.
VTU
N
O
TESBYSR
I

9
6 (b) Multiple 14×-8 using Booth's algorithm.(6 Marks)
Ans:
Solution:
6 (c) Explain normalization, excess-exponent and special values with respect to IEEE
floating point representation. (6 Marks)
Ans:
NORMALIZATION
• When the decimal point is placed to the right of the first(non zero) significant digit, the
number is said to be normalized (Figure: 6.25).
EXCESS-EXPONENT
• Instead of the signed exponent E, the value actually stored in the exponent field is an
unsigned integer E’=E+127 (Figure: 6.24).
• This is called the excess-127 format. Thus, E’ is in the range 0<=E’<=255. The end values
of this range 0 and 255 are used to represent special values.
SPECIAL VALUES
• The end values 0 and 255 of the excess-127 exponent E’ are used to represent special
values.
• When E’=0 and the mantissa fraction M is zero, the value exact 0 is represented.
• When E’=255 and M=0, the value ∞ is represented, where ∞ is the result of dividing a
normal number by zero.
• When E’=0 and M≠0, denormal numbers are represented. Their value is X2-126
• When E’=255 and M≠0, the value represented is called not a number(NaN). A NaN is the
result of performing an invalid operation such as 0/0 or
VTU
N
O
TESBYSR
I

10
7 (a) With a diagram, explain typical single bus processor data path.(8 Marks)
Ans:
SINGLE BUS ORGANIZATION
• MDR has 2 inputs and 2 outputs. Data may be loaded
→ into MDR either from memory-bus (external) or
→ from processor-bus (internal).
• MAR’s input is connected to internal-bus, and
MAR’s output is connected to external-bus.
• Instruction-decoder & control-unit is responsible for
→ issuing the signals that control the operation of all the units inside the processor
→ implementing the actions specified by the instruction (loaded in the IR)
• Registers R0 through R(n-1) are provided for general purpose use by programmer.
• Three registers Y, Z & TEMP are used by processor for temporary storage during execution of
some instructions. These are transparent to the programmer i.e. programmer need not be
concerned with them because they are never referenced explicitly by any instruction.
• MUX(Multiplexer) selects either
→ output of Y or
→ constant-value 4(is used to increment PC content). This is provided as input A of ALU.
• B input of ALU is obtained directly from processor-bus (Figure: 7.1).
• As instruction execution progresses, data are transferred from one register to another, often
passing through ALU to perform arithmetic or logic operation.
• An instruction can be executed by performing one or more of the following operations:
1) Transfer a word of data from one processor-register to another or to the ALU.
2) Perform arithmetic or a logic operation and store the result in a processor-register.
3) Fetch contents of a given memory-location and load them into a processor-register.
4) Store a word of data from a processor-register into a given memory-location.
VTU
N
O
TESBYSR
I

11
7 (b) Explain with neat diagram, the basic organization of a microprogrammed
control unit.(8 Marks)
7 (c) Differentials hardwired and microprogrammed control unit.(4 Marks)
Ans:
Micro Programmed Control
• Micro programmed control is a control mechanism to generate control signals by using a
memory called control storage (CS), which contains the control signals (Figure 7.2b).
Hard-wired Control
• Hardwired control is a control mechanism to generate control signals by using gates, flip-
flops, decoders, and other digital circuits (Figure 7.2a).
Figure 7.2a) Hardwired Figure 7.2b) microprogrammed control unit
Attribute Hardwired Control Microprogrammed Control
Speed Fast Slow
Control functions Implemented in hardware Implemented in software
Flexibility Not flexible to accommodate new
system specifications or new
instructions
More flexible, to accommodate
new system specification or new
instructions redesign is required
Ability to handle
large/complex
instruction sets
Difficult Easier
Ability to support
operating systems
and diagnostic
features
Very difficult Easy
Design process Complicated Orderly and systematic
Applications Mostly RISC microprocessors Mainframes, some
microprocessors
Instruction set size Usually under 100 instructions Usually over 100 instructions
ROM size - 2K to 10K by 20-400 bit
microinstructions
Chip area efficiency Uses least area Uses more area
VTU
N
O
TESBYSR
I

12
8 (a) Define and discuss Amdahl's law.(6 Marks)
Ans:
Amdahl's law
• Amdahl’s law says
• Suppose a program runs in 100 seconds on a computer, with multiply operations responsible
for 80 seconds of this time. How much do I have to improve the speed of multiplication if I
want my program to run five times faster
• For this problem:
• Since we want the performance to be five times faster, the new execution time should be 20
seconds, giving
• That is, there is no amount by which we can enhance-multiply to achieve a fivefold increase
in performance, if multiply accounts for only 80% of the workload
• We can use Amdahl’s law to estimate performance improvements when we know the time
consumed for some function and its potential speedup.
• Amdahl’s law is also used to argue for practical limits to the number of parallel processors.
8 (b) With a diagram, explain a shared memory multiprocessor architecture. (8
Marks)
8 (c) What is hardware multithreading? Explain the different approaches to
hardware multithreading. (6 Marks)
Ans:
• Hardware Multithreading: Increasing utilization of a processor by switching to another
thread when one thread is stalled
• There are two main approaches to hardware multithreading:
1) Fine-grained Multithreading & 2) Coarse-grained multithreading
i) Fine-grained Multithreading:
• A version of hardware multithreading that suggests switching between threads after every
instruction.
• This interleaving is often done in a round-robin fashion, skipping any threads that are stalled
at that time.
• Advantage:
→ It can hide the throughput losses that arise from both short and long stalls, since
instructions from other threads can be executed when one thread stalls.
• Disadvantage:
→ It slows down the execution of the individual threads, since a thread that is ready to
execute without stalls will be delayed by instructions from other threads.
ii) Coarse-grained Multithreading:
• A version of hardware multithreading that suggests switching between threads only after
significant events, such as a cache miss.
• This change relieves the need to have thread switching be essentially free and is much less
likely to slow down the execution of an individual thread, since instructions from other threads
will only be issued when a thread encounters a costly stall.
• Disadvantage:
→ It is limited in its ability to overcome throughput losses, especially from shorter stalls.
• Advantage:
→ It is much more useful for reducing the penalty of high-cost stalls, where pipeline refill
is negligible compared to the stall time.
VTU
N
O
TESBYSR
I

1
1 a. With a neat diagram, explain the different processor registers. (08 Marks)
1 b. List and explain the technological features and devices improvement made
during different generations of computers. (08 Marks)
Ans:
FIRST GENERATION (1945-1955)
• Program and data reside in the same memory (stored program concepts – John von
Neumann).
• ALP was made used to write programs.
• Vacuum tubes were used to implement the functions (ALU & CU design).
• Magnetic core and magnetic tape storage devices are used.
• Using electronic vacuum tubes, as the switching components.
SECOND GENERATION(1955–1965)
• Transistor were used to design ALU & CU.
• HLL is used (FORTRAN).
• To convert HLL to MLL compiler were used.
• Separate I/O processor were developed to operate in parallel with CPU, thus improving the
performance.
• Invention of the transistor which was faster, smaller and required considerably less power to
operate.
THIRD GENERATION(1965‐1975)
• IC technology improved.
• Improved IC technology helped in designing low cost, high speed processor and memory
modules.
• Multiprogramming, pipelining concepts were incorporated.
• DOS allowed efficient and coordinate operation of computer system with multiple users.
• Cache and virtual memory concepts were developed.
• More than one circuit on a single silicon chip became available.
FOURTH GENERATION(1975‐1985)
• CPU – Termed as microprocessor.
• INTEL, MOTOROLA, TEXAS,NATIONAL semiconductors started developing microprocessor.
• Workstations, microprocessor (PC) & Notebook computers were developed.
• Interconnection of different computer for better communication LAN,MAN,WAN.
• Computational speed increased by 1000 times.
• Specialized processors like Digital Signal Processor were also developed.
BEYOND THE FOURTH GENERATION (1985 – TILL DATE)
• E‐Commerce, E‐ banking, home office.
• ARM, AMD, INTEL, MOTOROLA.
• High speed processor ‐ GHz speed.
• Because of submicron IC technology lot of added features in small size.
1 c. What are the factors that affect the Performance? Explain any four. (04 Marks)
Ans:
PERFORMANCE
• Performance means time taken by the system to execute a program
• Parameters which influence the performance are:
→ Clock speed.
→ Type and number of instructions available.
→ Average time required to execute an instruction.
→ Memory access time.
→ Power dissipation in the system.
→ Number of I/O devices and types of I/O devices connected.
→ The data transfer capacity of the bus.
2 a. What is an addressing mode? Explain any four addressing modes, with an
example for each. (08 Marks)
VTU
N
O
TESBYSR
I

2
2 b. Explain i) rotate and ii) shift operations with example. (08 Marks)
Ans i): For answer, refer Solved Paper June-2014 Q.No.2b
Ans ii):
SHIFT INSTRUCTIONS
• There are many applications that require the bits of an operand to be shifted right or left
some specified number of bit positions.
• The details of how the shifts are performed depend on whether the operand is a signed
number or some more general binary-coded information.
• For general operands, we use a logical shift.
For a number, we use an arithmetic shift, which preserves the sign of the number.
LOGICAL SHIFTS
• Two logical shift instructions are needed, one for shifting left(LShiftL) and another for
shifting right(LShiftR).
• These instructions shift an operand over a number of bit positions specified in a count
operand contained in the instruction (Figure 2.30).
VTU
N
O
TESBYSR
I

3
2 c. Explain big-endian & little-endian method of byte addressing with eg (04 Marks)
Ans:
BIG-ENDIAN AND LITTLE-ENDIAN ASSIGNMENTS
• There are two ways in which byte addresses are arranged.
1) Big-endian assignment: lower byte addresses are used for the more significant
bytes of the word (Figure 2.7).
2) Little-endian: lower byte addresses are used for the less significant bytes of the
word
• In both cases, byte addresses 0, 4, 8. . . . . are taken as the addresses of successive words
in the memory.
3 a. Define Exceptions. Explain two kinds of exceptions. (04 Marks)
Ans:
EXCEPTIONS
• Exception refers to any event that causes an interruption.
• I/O interrupts are one example of an exception.
Recovery from Errors
• Computers use a variety of techniques to ensure that all hardware-components are
operating properly. For e.g. many computers include an error-checking code in main-memory
which allows detection of errors in stored-data.
• If an error occurs, control-hardware detects it & informs processor by raising an interrupt.
• When exception processing is initiated (as a result of errors), processor
→ suspends program being executed &
→ starts an ESR(Exception Service Routine). This routine takes appropriate action to
recover from the error to inform user about it.
Debugging
• Debugger
→ helps programmer find errors in a program and
→ uses exceptions to provide 2 important facilities: 1) Trace & 2) Breakpoints
• When a processor is operating in trace-mode, an exception occurs after execution of every
instruction (using debugging-program as ESR).
• Debugging-program enables user to examine contents of registers (AX, BX), memory-
locations and so on.
• On return from debugging-program,
next instruction in program being debugged is executed,
then debugging-program is activated again.
• Breakpoints provide a similar facility except that program being debugged is interrupted only
at specific points selected by user. An instruction called Trap(or Software interrupt) is usually
provided for this purpose.
3 b. Define bus arbitration. Explain any approach of bus arbitration.(08 Marks)
VTU
N
O
TESBYSR
I

4
3 c. Draw and explain the general 8 bit parallel processing. (08 Marks)
Ans:
• Data lines P7 through PO can be used for either input or output purposes (Figure 4.34).
• For increased flexibility, the circuit makes it possible for some lines to serve as inputs and
some lines to serve as outputs, under program control.
• The DATAOUT register is connected to these lines via three-state drivers that are controlled
by a data direction register, DDR.
• The processor can write any 8-bit pattern into DDR.
• For a given bit, if the DDR value is 1, the corresponding data line acts as an output line;
otherwise, it acts as an input line.
• Two lines, C1 and C2, are provided to control the interaction between the interface circuit
and the I/0 device it serves.
• Line C2 is bidirectional to provide several different modes of signaling, including the
handshake.
• The Ready and Accept lines are the handshake control lines on the processor bus side, and
hence would be connected to Master-ready and Slave-ready.
• The input signal My-address should be connected to the output of an address decoder that
recognizes the address assigned to the interface.
• There are three register select lines, allowing up to eight registers in the interface, input and
output data, data direction, and control and status registers for various modes of operation.
• An interrupt request output, INTR, is also provided.
• It should be connected to the interrupt-request line on the computer bus.
4 a. Explain the following with respect to USB: i) USB Architecture ii) USB
Addressing iii) USB Protocols. (09 Marks)
Ans: i) For answer, refer Solved Paper June-2014 Q.No.4b
Ans: ii) For answer, refer Solved Paper June-2014 Q.No.4b
Ans: iii) For answer, refer Solved Paper June-2013 Q.No.4c
VTU
N
O
TESBYSR
I

5
4 b. Briefly discuss main phases involved in the operation of SCSI bus. (06 Marks)
Ans:
PHASES IN SCSI BUS
• The phases in SCSI bus operation are:
i) Arbitration
ii) Selection
iii) Information transfer
iv) Reselection
i) Arbitration
• When the –BSY signal is in inactive state, the bus will he free & any controller can request
the use of the bus.
• Since each controller may generate requests at the same time, SCSI uses distributed
arbitration scheme.
• Each controller on the bus is assigned a fixed priority with controller 7 having the highest
priority.
• When –BSY becomes active, all controllers that are requesting the bus examines the data
lines & determine whether the highest priority device is requesting the bus at the same time.
• The controller using the highest numbered line realizes that it has won the arbitration
process.
• At that time, all other controllers disconnect from the bus & wait for –BSY to become inactive
again.
ii) Information Transfer
• The information transferred between two controllers may consist of
→ commands from the initiator to the target,
→ status responses from the target to the initiator, or
→ data being transferred to or from the I/0 device.
• Handshake signaling is used to control information transfers, with the target controller taking
the role of the bus master.
iii) Selection
• Here Device wins arbitration and it asserts –BSY and –DB6 signals (Figure 4.42).
• The Select Target Controller responds by asserting –BSY.
• This informs that the connection that it requested is established.
iv) Reselection
• The connection between the two controllers has been reestablished, with the target in
control the bus as required for data transfer to proceed.
4 c. Explain distributed bus arbitration. (05 Marks)
VTU
N
O
TESBYSR
I

6
5 a. Define : i) Memory Latency ii) Memory bandwidth
iii) Hit - rate iv) Miss Penalty. (04 Marks)
Ans:
i) Latency
• It refers to the amount of time it takes to transfer a word of data to or from the memory.
• For a transfer of single word, the latency provides the complete indication of memory
performance.
• For a block transfer, the latency denote the time it takes to transfer the first word of data.
ii) Bandwidth
• It is defined as the number of bits or bytes that can be transferred in one second.
• Bandwidth mainly depends upon the speed of access to the stored data & on the number of
bits that can be accessed in parallel.
iii) Hit rate
• The number of hits stated as a fraction of all attempted accesses is called the hit rate.
iv) Miss penalty
• The extra time needed to bring the desired information into the cache is called the miss
penalty.
5 b. Explain the different cache mapping functions. (10 Marks)
5 c. Explain any one feature of memory design that leads to improved performance
of computer. (06 Marks)
Ans: For answer, refer Solved Paper June-2013 Q.No.5c
VTU
N
O
TESBYSR
I

7
6 a. With a neat diagram, explain the virtual memory organization. (08 Marks)
Ans:
• Techniques that automatically move program and data blocks into the physical main memory
when they are required for execution are called virtual-memory techniques.
• The processor reference an instruction and data space that is independent of the available
physical main memory space (Figure 5.26).
• The binary addresses that the processor issues for either instructions or data are called
virtual or logical addresses.
• These addresses are translated into physical addresses by a combination of hardware and
software components.
• If a virtual address refers to a part of the program or data space that is currently in the
physical memory, then the contents of the appropriate location in the main memory are
accessed immediately.
• On the other hand, if the referenced address is not in the main memory, its contents must
be brought into a suitable location in the memory before they can be used.
• A special hardware unit, called the Memory Management Unit (MMU), translates virtual
addresses into physical addresses.
• When the desired data (or instructions) are in the main memory, these data are fetched.
• If the data are not in the main memory, the MMU causes the operating system to bring the
data into the memory from the disk.
• Transfer of data between the disk and the main memory is performed using the DMA
scheme.
VTU
N
O
TESBYSR
I

8
6 b. Design a logic circuit to perform addition/subtraction of two ‘n' bit numbers X
and Y. (04 Marks)
Ans:
• The n-bit adder can be used to add 2's complement numbers X and Y (Figure 6.3).
• Overflow can only occur when the signs of the 2 operands are the same.
• In order to perform the subtraction operation X-Y on 2's complement numbers X and Y; we
form the 2's complement of Y and add it to X.
• Addition or subtraction operation is done based on value applied to the Add/Sub input
control-line.
• Control-line=0 for addition, applying the Y vector unchanged to one of the adder inputs.
Control-line=1 for subtraction, the Y vector is 2's complemented.
6 c. Explain Booth Algorithm. Apply Booth Algorithm to multiply the signed numbers
+13 and -6. (08 Marks)
Ans:
BOOTH ALGORITHM
• This algorithm
→ generates a 2n-bit product
→ treats both positive & negative 2's-complement n-bit operands uniformly.
• Attractive feature: This algorithm achieves some efficiency in the number of addition
required when the multiplier has a few large blocks of 1s.
• This algorithm suggests that we can reduce the number of operations required for
multiplication by representing multiplier as a difference between 2 numbers.
For e.g. multiplier(Q) 14(001110) can be represented as
010000 (16)
-000010 (2)
001110 (14)
• Therefore, product P=M*Q can be computed by adding 24 times the M to the 2's
complement of 21 times the M.
Solution:
VTU
N
O
TESBYSR
I

9
7 a. Explain different arithmetic operations on floating point numbers. (06 Marks)
Ans:
ARITHMETIC OPERATIONS ON FLOATING-POINT NUMBERS
Multiply Rule
1) Add the exponents & subtract 127.
2) Multiply the mantissas & determine sign of the result.
3) Normalize the resulting value if necessary.
Divide Rule
1) Subtract the exponents & add 127.
2) Divide the mantissas & determine sign of the result.
Add/Subtract Rule
1) Choose the number with the smaller exponent & shift its mantissa right a number of steps
equal to the difference in exponents(n).
2) Set exponent of the result equal to larger exponent.
3) Perform addition/subtraction on the mantissas & determine sign of the result.
7 b. Perform division of number 8 by 3 (8 + 3) using the restoring division algorithm.
(06 Marks)
Ans:
• Procedure: Do the following n times
1) Shift A and Q left one binary position (Figure 6.22).
2) Subtract M from A, and place the answer back in A
3) If the sign of A is 1, set q0 to 0 and add M back to A(restore A).
If the sign of A is 0, set q0 to 1 and no restoring done.
c
VTU
N
O
TESBYSR
I

10
7 c. Explain the process of fetching a word from memory along with a timing
diagram. (08 Marks)
Ans:
FETCHING A WORD FROM MEMORY
• To fetch instruction/data from memory, processor transfers required address to MAR (whose
output is connected to address-lines of memory-bus).
At the same time, processor issues Read signal on control-lines of memory-bus.
• When requested-data are received from memory, they are stored in MDR. From MDR, they
are transferred to other registers (Figure 7.4).
• MFC (Memory Function Completed): Addressed-device sets MFC to 1 to indicate that the
contents of the specified location
→ have been read &
→ are available on data-lines of memory-bus
• Consider the instruction Move (R1),R2. The sequence of steps is:
1) R1out, MARin, Read ;desired address is loaded into MAR & Read command is issued
2) MDRinE, WMFC ;load MDR from memory bus & Wait for MFC response from memory
3) MDRout, R2in ;load R2 from MDR
where WMFC=control signal that causes processor's control
circuitry to wait for arrival of MFC signal
8 a. Briefly explain the structure of General Purpose Multiprocessor. (08 Marks)
VTU
N
O
TESBYSR
I

11
8 b. List different types of Networks. Explain any four. (08 Marks)
Ans:
LAN (Local Area Network)
• A LAN is a network that is used for communicating among computer devices, usually within
an office building or home.
• LAN’s enable the sharing of resources such as files or hardware devices that may be needed
by multiple users.
• Is limited in size, typically spanning a few hundred meters, and no more than a mile.
• Is fast, with speeds from 10 Mbps to 10 Gbps.
• Requires little wiring, typically a single cable connecting to each device.
• Has lower cost compared to MAN’s or WAN’s.
• LAN’s can be either wired or wireless. Twisted pair, coax or fibre optic cable can be used in
wired LAN’s.
• Nodes in a LAN are linked together with a certain topology. These topologies include:
– Bus
– Ring
– Star
• LANs are capable of very high transmission rates (100s Mb/s to Gbps).
MAN (Metropolitan Area Network)
• A metropolitan area network (MAN) is a large computer network that usually spans a city or
a large campus.
• A MAN is optimized for a larger geographical area than a LAN, ranging from several blocks of
buildings to entire cities.
• A MAN might be owned and operated by a single organization, but it usually will be used by
many individuals and organizations.
• A MAN often acts as a high speed network to allow sharing of regional resources.
• A MAN typically covers an area of between 5 and 50 km diameter.
• Examples of MAN: Telephone company network that provides a high speed DSL to customers
and cable TV network.
WAN (Wide Area Network)
• WAN covers a large geographic area such as country, continent or even whole of the world.
• A WAN is two or more LANs connected together. The LANs can be many miles apart.
• To cover great distances, WANs may transmit data over leased high-speed phone lines or
wireless links such as satellites.
• Multiple LANs can be connected together using devices such as bridges, routers, or
gateways, which enable them to share data.
• The world's most popular WAN is the Internet.
PAN (Personal Area Network)
• A PAN is a network that is used for communicating among computers and computer devices
(including telephones) in close proximity of around a few meters within a room
• It can be used for communicating between the devices themselves, or for connecting to a
larger network such as the internet.
• PAN’s can be wired or wireless.
• A personal area network (PAN) is a computer network used for communication among
computer devices, including telephones and personal digital assistants, in proximity to an
individual's body.
• The devices may or may not belong to the person in question. The reach of a PAN is typically
a few meters.
VTU
N
O
TESBYSR
I

12
8 c. Give a brief description on performance consideration with an e.g. (04 Marks)
Ans:
VTU
N
O
TESBYSR
I

VTU 4TH SEM CSE COMPUTER ORGANIZATION SOLVED PAPERS OF JUNE-2013 JUNE-2014 & JUNE-2015

Recommended

Recommended

More Related Content

What's hot

What's hot (20)

Similar to VTU 4TH SEM CSE COMPUTER ORGANIZATION SOLVED PAPERS OF JUNE-2013 JUNE-2014 & JUNE-2015

Similar to VTU 4TH SEM CSE COMPUTER ORGANIZATION SOLVED PAPERS OF JUNE-2013 JUNE-2014 & JUNE-2015 (20)

More from vtunotesbysree

More from vtunotesbysree (15)

Recently uploaded

Recently uploaded (20)

VTU 4TH SEM CSE COMPUTER ORGANIZATION SOLVED PAPERS OF JUNE-2013 JUNE-2014 & JUNE-2015