The document discusses MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors), specifically n-channel enhancement mode MOSFETs. It covers the basic structure and operation of MOSFETs including the different regions of operation (cut-off, triode, saturation), threshold voltage, I-V characteristics, and how scaling down the channel length and oxide thickness impacts device performance.

1. MOSFETs
Metal-Oxide-Semiconductor
Field Effect Transistors

2. Classes of Field Effect Transistors
• Metal-Oxide-Semiconductor Field Effect Transistor
– Which will be the type that we will study in this course.
• Metal-Semiconductor Field Effect Transistor
– MESFET
• Junction Field Effect Transistor
– JFET
• High Electron Mobility Transistor or Modulation Doped
Field Effect Transistor
– HEMT or MODFET
• Fast Reverse/Fast Recovery Epitaxial Diode
– FREDFET
• DNA Field Effect Transistor
– The conduction path is through a strand of DNA

3. Field Effect Transistors
• The conductivity (or resistivity) of the path
between two contacts, the source and the
drain, is altered by the voltage applied to
the gate.
– Device is also known as a voltage controlled
resistor.

4. Types of MOSFETS
n-channel
Enhancement Mode
(nMOSFET)
p-channel
Enhancement Mode
(pMOSFET)
n-channel
Depletion Mode
(nMOSFET)
p-channel
Depletion Mode
(pMOSFET)

5. Cross-Sectional View of n channel
planar Enhancement Mode Transistor

6. p channel
Enhancement Mode Transistor

7. n channel
Depletion Mode Transistor

8. p channel
Depletion Mode Transistor

9. Symbols for n channel
Enhancement Mode MOSFET
VGS ≥ 0V, VDS ≥ 0V
VTN is positive

10. Symbols for p channel
Enhancement Mode MOSFET
VGS ≤ 0V, VDS ≤ 0V
VTP is negative

11. Symbols for n channel
Depletion Mode MOSFET

12. Symbols for p channel
Depletion Mode MOSFET

13. PSpice MOSFET Symbols
• The IRF150 is an nMOS and the IRF9140 is a pMOS.
Both are enhancement mode transistors.
– The body terminal is connected to the source terminal on
the FET.
– “M” is used to denote that the device is a MOSFET.

14. MOS Capacitor

15. MOS Capacitor Under Bias:
Electric Field and Charge
Parallel plate capacitor
Accumulation
Positive gate bias
Electrons attracted to gate

16. Depletion Inversion
Negative gate bias:
Holes attracted to gate

17. MOS Capacitor:
p-type semiconductor
Accumulation Depletion Inversion

18. Threshold Voltage
The gate voltage that causes the concentration of electrons
immediately under the gate oxide is equal to the
concentration of holes is called the threshold voltage.
• Enhancement mode FETs
• NMOS VG = VTN
• When enough electrons have been attracted to the oxide-semiconductor interface to
create a path for current to flow between the source and drain.
• PMOS VG = VTP
• When holes have been attracted to the oxide-semiconductor interface to create a path
for current to flow between the source and drain.
• Depletion mode FETs
• NMOS VG = VTN
• When holes have been attracted to the oxide-semiconductor interface to stop current
from flowing between the source and drain.
• PMOS VG = VTP
• When electrons have been attracted to the oxide-semiconductor interface to stop
current from flowing between the source and drain.

19. Capacitance
OX
ox
OX
ox
OX
OX
OX
T
T
C
A
C
C
C






"
"
Region,
on
Accumulati
In
http://ecee.colorado.edu/~bart/book/

20. MOSFETs
Enhancement mode Depletion mode
• Also known as Normally
Off transistors.
– A voltage must be applied
to the gate of the transistor,
at least equal to the
threshold voltage, to create
a conduction path between
the source and the drain of
the transistor before current
can flow between the
source and drain.
• Also known as Normally
On transistors.
– A voltage must be applied
to the gate of the transistor,
at least equal to the
threshold voltage, to
destroy a conduction path
between the source and
the drain of the transistor to
prevent current from
flowing between the source
and drain.

21. Before electron
inversion layer is
formed
After electron
inversion layer is
formed

22. Family of ID Versus VDS Curves:
Enhancement-Mode nMOSFET
VDS > VGS – VTN
VDS < VGS – VTN
Pinch-off/Saturation
Triode/
Nonsaturation
Cut-off VGS < VTN

23. Family of iD Versus vDS Curves:
Depletion-Mode nMOSFET
Assuming that VTN < -1V

24. For this discussion
• I am going to emphasize the operation and
applications of n channel enhancement
mode FETs

25. Piecewise Model
Cut-off Region
VGS < VTN
VTN is positive
ID = 0 mA

26. Piecewise Model
Nonsaturation/Triode Region
VGS > VTN
VDS < VGS – VTN
ID ≤ 0 mA
VTN is positive

27. Piecewise Model
Saturation/Pinch-off Region
VGS > VTN
VDS > VGS – VTN
ID ≤ 0 mA
VTN is positive

28. Summary of I-V Relationships
Region NMOS
Nonsaturation/
Triode
VDS < VDS(sat)
Saturation/
Pinch-off
VDS > VDS(sat)
Transition between triode
and pinch-off
VDS(sat) = VGS - VTN
Enhancement Mode VTN > 0 V, ID ≥ 0 mA, ID = IS, IG = 0 mA
D
DS
DSon
DS
DS
TN
GS
n
D
I
V
R
V
V
V
V
L
W
k
I
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
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




 2
'
2
1
)
(
2
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]
[
2
TN
GS
n
D V
V
L
W
k
I 



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

29. Questions
• To increase the drain current ID at a particular VDS and VGS, should
you use a MOSFET with a larger or smaller W/L ratio?
• Compare the operation of two FETs, where MOS #1 has a smaller
VTN than MOS #2. Sketch the differences on a graph of ID-VDS.
• The microelectronics industry is working to decrease the channel
length L. If W is held constant, how will:
– the capacitance between the gate and the channel change?
– the time it takes for an electron to move from the source to the drain be altered?
– the value of VTN change?
– this modify RDSon for a particular set of VDS and VGS?
• The microelectronics industry is also working to decrease the
thickness of the gate oxide TOX and is researching high  and low 
dielectrics to replace silicon dioxide as the gate dielectric?
– If TOX decreases, how will the capacitance between the gate and channel
change?
– Should a low  or high  dielectric be used to increase the capacitance?