The document discusses the challenges of validating next generation CPUs. It notes that validation is increasingly critical for product success but requires constant innovation. Design complexity is growing exponentially, requiring up to 70% of resources for functional validation. The number of pre-silicon logic bugs found per generation has also increased significantly. Shorter timelines and cross-site development further complicate the validation process.

1. Validating next generation CPUs Praveen Vishakantaiah President, Intel India Feb 22, 2008 DV Club Bangalore

2. “ Validation is increasingly in the critical path of product success and requires continuous innovation to meet customer satisfaction, schedule and margin requirements”

3. Agenda Current Challenges Addressing the challenges

4. CPU bug trends Exponential growth of design complexity Deeply pipelined complex micro-architecture Logic bugs increase 3 - 4x per generation Up to 70% of design time and resources are spent during functional validation Pre-silicon logic bugs per generation ( Source : Tom Schubert, Intel, DAC 2003 ) 7855 2240 800 25000 Pentium Pentium Pro Pentium 4 Next ?

5. The Pre-Si Verification gap EE Times 03/18/2004 Verification Capabilities is fast becoming the limiting factor for VLSI design improvements EE Times 2004

6. Current Challenges – Technical Increasing CPU design complexity Multi core Chipset integration Power Management New technology like security Increasingly bulky validation environment Increase in development and maintenance cost Environment bugs >= Logic design bugs Increasing number of product variants Validation is not as incremental as design Increasing micro-architectural coverage space increases probability of escapes Decreasing simulation/emulation speed limits pre-silicon cycles Legacy features and compatibility validation High volumes magnify the cost of a validation escape – can not let it happen!

7. Current Challenges – Non-Technical Shorter TTM (Time to Market) Physical limits and cost of data centers CPU validation expertise More pronounced in India due to frequent job changes Cross site development Design and validation may not be co-located

8. Post-silicon validation SOC and Multi core leverage incremental design effort Design interactions are spatial in nature Effective design reuse is possible Post Si Validation efforts currently not scaling incrementally - Logic interactions across widely separated areas introduces unexpected bugs - No effective coverage feedback mechanism - When is Validation enough ? - Synthesis of approx coverage measure - Effective Mathematical Models

9. Addressing the challenges Use experienced architects, micro-architects and front end designers Very likely to have lot more validation “burn” marks and will proactively code less bugs Will be able to help validators debug issues faster Raise the watermark for bugs and reduce iterations Validators drive requirements into architecture and micro-architecture Influence technology decisions to keep validation tractable Minimize feature creep during execution Reduce back end design impact on front end design Instrument design models to enable validation Assertions, instrumentation signals, comments Aim for sweet spot with Effectiveness vs. Efficiency trade offs Validation Environment Minimize custom tool development Reuse design, validation and debug tools across programs Scale emulation, formal verification and mixed signal validation

10. Validation coverage profile and Efficacy Probability of bugs Time Si Spin1 Si Spin2 Efficiency: Catch bugs fast Effectiveness: Catch all customer visible bugs Early detection and bug acceleration has significant business benefits

11. Q&A